Datenblatt-Suchmaschine für elektronische Bauteile |
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CD4033 Datenblatt(PDF) 1 Page - Intersil Corporation |
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CD4033 Datenblatt(HTML) 1 Page - Intersil Corporation |
1 / 11 page 7-826 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 CD4033BMS CMOS Decade Counter/Divider Description CD4033BMS consists of a 5 stage Johnson decade counter and an output decoder which converts the Johnson code to a 7 segment decoded output for driving one stage in a numerical display. This device is particularly advantageous in display applications where low power dissipation and/or low package count is important. A high RESET signal clears the decade counter to its zero count. The counter is advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the CLOCK INHIBIT signal is high. The CLOCK INHIBIT signal can be used as a negative-edge clock if the clock line is held high. Antilock gating is provided on the JOHNSON counter, thus assuring proper counting sequence. The CARRY-OUT (Cout) signal completes one cycle every ten CLOCK INPUT cycles and is used to clock the succeeding decade directly in a multi-decade counting chain. The seven decoded outputs (a, b, c, d, e, f, g) illuminate the proper segments in a seven segment display device used for representing the decimal numbers 0 to 9. The 7 segment out- puts go high on selection. Features • High Voltage Types (20V Rating) • Decoded 7 Segment Display Outputs and Ripple Blanking • Counter and 7 Segment Decoding in One Package • Easily Interfaced with 7 Segment Display Types • Fully Static Counter Operation DC to 6MHz (typ.) at VDD = 10V • Ideal for Low-Power Displays • “Ripple Blanking” and Lamp Test • 100% Tested for Quiescent Current at 20V • Standardized Symmetrical Output Characteristics • 5V, 10V and 15V Parametric Ratings • Schmitt-Triggered Clock Inputs • Meets All Requirements of JEDEC Tentative Stan- dards No. 13B, “Standard Specifications for Descrip- tion of “B” Series CMOS Device’s Applications • Decade Counting 7 Segment Decimal Display • Frequency Division 7 Segment Decimal Displays • Clocks, Watches, Timers (e.g. ÷ 60, ÷ 60, ÷12 Counter/ Display • Counter/Display Driver For Meter Applications File Number 3301 December 1992 Pinout CD4033BMS TOP VIEW 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 CLOCK CLOCK INHIBIT RIPPLE BLANKING IN RIPPLE BLANKING OUT CARRY OUT f VSS g VDD LAMP TEST c b e a d RESET Functional Diagram CLOCK b c d e f g CARRY OUT RIPPLE VSS VDD 110 12 13 9 11 6 7 5 16 8 a 4 BLK OUT 3 RIPPLE BLK IN 2 15 CLOCK INHIBIT RESET 14 LAMP TEST |
Ähnliche Teilenummer - CD4033 |
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Ähnliche Beschreibung - CD4033 |
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