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AD7868 Datenblatt(PDF) 6 Page - Analog Devices |
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AD7868 Datenblatt(HTML) 6 Page - Analog Devices |
6 / 16 page AD7868 –6– REV. B CONVERTER DETAILS The AD7868 is a complete 12-bit I/O port, the only external components required for normal operation are pull-up resistors for the ADC data outputs and power supply decoupling capaci- tors. It is comprised of a 12-bit successive approximation ADC with a track/hold amplifier, a 12-bit DAC with a buffered output and two 3 V buried Zener references, a clock oscillator and con- trol logic. ADC CLOCK The AD7868 has an internal clock oscillator which can be used for the ADC conversion procedure. The oscillator is enabled by tying the CLK input to VSS. The oscillator in laser trimmed at the factory to give a conversion time of between 8.5 and 10 µs. The mark/space ratio can vary from 40/60 to 60/40. Alterna- tively, an external TTL compatible clock may be applied to this input. The allowable mark/space ratio of an external clock is 40/60 to 60/40. RCLK is a clock output, used for the serial in- terface. This output is derived directly from the ADC clock source and can be switched off at the end of conversion with the CONTROL input. ADC CONVERSION TIMING The conversion time for both external clock and continuous in- ternal clock can vary from 19 to 20 rising clock edges depending on the conversion start to ADC clock synchronization. If a con- version is initiated within 30 ns prior to a rising edge of the ADC clock, the conversion time will consist of 20 rising clock edges, i.e., 9.5 µs conversion time. For noncontinuous internal clock, the conversion time is always 19 rising clock edges. ADC TRACK-AND-HOLD AMPLIFIER The track-and-hold amplifier on the analog input of the AD7868 allows the ADC to accurately convert an input sine wave of 6 V peak–peak amplitude to 12-bit accuracy. The input impedance is typically 9 k Ω, an equivalent circuit is shown in Figure 1. The input bandwidth of the track/hold amplifier is much greater than the Nyquist rate of the ADC, even when the ADC is operated at its maximum throughput rate. The 0.1 dB cutoff frequency oc- curs typically at 500 kHz. The track/hold amplifier acquires an input signal to 12-bit accuracy in less than 2 µs. AD7868* 4.5k Ω *ADDITIONAL PINS OMITTED FOR CLARITY VIN TO INTERNAL COMPARATOR TRACK/HOLD AMPLIFIER TO INTERNAL 3V REFERENCE 4.5k Ω Figure 1. ADC Analog Input The overall throughput rate is equal to the conversion time plus the track/hold amplifier acquisition time. For a 2.0 MHz input clock the throughput time is 12 µs max. The operation of the track/hold amplifier is essentially transpar- ent to the user. The track/hold amplifier goes from its track mode to its hold mode at the start of conversion on the rising edge of CONVST. INTERNAL REFERENCES The AD7868 has two on-chip temperature compensated buried Zener references which are factory trimmed to 3 V ± 10 mV. One reference provides the appropriate biasing for the ADC, while the other is available as a reference of the DAC. Both ref- erence outputs are available (labeled RO DAC and RO ADC) and are capable of providing up to 500 µA to an external load. The DAC input reference (RI DAC) can be stored externally or connected to any of the two on-chip references. Applications requiring good full-scale error matching between the DAC and the ADC should use the ADC reference as shown in Figure 4. The maximum recommended capacitance on either of the refer- ence output pins for normal operation is 50 pF. If either of the reference outputs is required to drive a capacitive load greater than 50 pF, then a 200 Ω resistor must be placed in series with the capacitive load. The addition of decoupling capacitors, 10 µF in parallel with 0.1 µF, as shown in Figure 2, improves noise performance. The improvement in noise performance can be seen from the graph in Figure 3. Note, this applies for the DAC output only; reference decoupling components do not af- fect ADC performance. So, a typical application will have just the DAC reference source decoupled with the other one open circuited. RI DAC 200 Ω 10 µF 0.1 µF RO DAC or RO ADC* EXT LOAD GREATER THAN 50pF *RO DAC/RO ADC CAN BE LEFT OPEN CIRCUIT IF NOT USED Figure 2. Reference Decoupling Circuitry DAC OUTPUT AMPLIFIER The output from the voltage-mode DAC is buffered by a nonin- verting amplifier. The buffer amplifier is capable of developing ±3 V across 2 kΩ and 100 pF load to ground and can produce 6 V peak-to-peak sine wave signals to a frequency of 20 kHz. The output is updated on the falling edge of the LDAC input. The output voltage settling time, to within 1/2 LSB of its final value, is typically less than 2 µs. The small signal (200 mV p-p) bandwidth of the output buffer amplifier is typically 1 MHz. The output noise from the ampli- fier is low with a figure of 30 nV/ √Hz at a frequency of 1 kHz. The broadband noise from the amplifier exhibits a typical peak- to-peak figure of 150 µV for a 1 MHz output bandwidth. Fig- ure 3 shows a typical plot of noise spectral density versus fre- quency for the output buffer amplifier and for either of the on-chip references. |
Ähnliche Teilenummer - AD7868_15 |
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Ähnliche Beschreibung - AD7868_15 |
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