7-444

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

CD4071BMS, CD4072BMS

CD4075BMS

CMOS OR Gate

Pinout

CD4071BMS

TOP VIEW

CD4072BMS

TOP VIEW

CD4075BMS

TOP VIEW

A

B

J = A + B

K = C + C

C

D

VSS

VDD

H

G

M = G + H

L = E + F

F

E

1

2

3

4

5

6

7

14

13

12

11

10

9

8

J = A + B + C + D

A

B

C

D

NC

VSS

VDD

K = E +F + G + H

H

G

F

E

NC

1

2

3

4

5

6

7

14

13

12

11

10

9

8

NC = NO CONNECTION

A

B

D

E

F

K = D + E + F

VSS

VDD

G

H

I

L = G + H + I

J = A + B + C

C

1

2

3

4

5

6

7

14

13

12

11

10

9

8

Features

• High-Voltage Types (20V Rating)

• CD4071BMS Quad 2-Input OR Gate

• CD4072BMS Dual 4-Input OR Gate

• CD4075BMS Triple 3-Input OR Gate

• Medium Speed Operation:

- tPHL, tPLH = 60ns (typ) at 10V

• 100% Tested for Quiescent Current at 20V

• Maximum Input Current of 1

µA at 18V Over Full Pack-

• Standardized Symmetrical Output Characteristics

• Noise Margin (Over Full Package Temperature Range):

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• 5V, 10V and 15V Parametric Ratings

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Specifications for Description of

‘B’ Series CMOS Devices”

Description

CD4071BMS, CD4072BMS and CD4075BMS OR gates pro-

vide the system designer with direct implementation of the

positive-logic OR function and supplement the existing fam-

ily of CMOS gates.

The CD4071BMS, CD4072BMS and CD4075BMS are supplied

in these 14 lead outline packages:

Braze Seal DIP

*H4H

†H4Q

Frit Seal DIP

H1B

Ceramic Flatpack

H3W

*CD4071, CD4072

†CD4075 Only

File Number

3323

December 1992