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CD4536BMS Datenblatt(PDF) 1 Page - Intersil Corporation |
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CD4536BMS Datenblatt(HTML) 1 Page - Intersil Corporation |
1 / 13 page 7-1236 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 CD4536BMS CMOS Programmable Timer Description CD4536BMS is a programmable timer consisting of 24 ripple binary counter stages. The salient feature of this device is its flexibility. The device can count from 1 to 224 or the first 8 stages can be bypassed to allow an output, selectable by a 4-bit code, from any one of the remaining 16 stages. It can be driven by an external clock or an RC oscillator that can be constructed using on-chip components. Input IN1 serves as either the external clock input or the input to the on-chip RC oscillator. OUT1 and OUT2 are connection terminals for the external RC components. In addition, an on-chip monostable circuit is provided to allow a variable pulse width output. Var- ious timing functions can be achieved using combinations of these capabilities. A logic 1 on the 8-BYPASS input enables a bypass of the first 8 stages and makes stage 9 the first counter stage of the last 16 stages. Selection of 1 of 16 outputs is accom- plished by the decoder and the BCD inputs A, B, C and D. MONO IN is the timing input for the on-chip monostable oscillator. Grounding of the MONO IN terminal through a resistor of 10k Ω or higher, disables the one-shot circuit and connects the decoder directly to the DECODE OUT terminal. A resistor to VDD and a capacitor to ground from the MONO IN terminal enables the one-shot circuit and controls its pulse width. A fast test mode is enabled by a logic 1 on 8-BYPASS, SET, and RESET. This mode divides the 24-stage counter into three 8-stage sections to facilitate a fast test sequence. The CD4536BMS is supplied in these 16-lead outline packages: Braze Seal DIP H4X Frit Seal DIP H1F Ceramic Flatpack H6W Features • High Voltage Type (20V Rating) • 24 Flip-Flop Stage - Counts from 20 to 224 • Last 16 Stages Selectable by BCD Select Code • Bypass Input Allows Bypassing First 8 Stages • On-Chip RC Oscillator Provision • Clock Inhibit Input • Schmitt Trigger in clock Line Permits Operation with Very Long Rise and Fall Times • On-Chip Monostable Output Provision • Typical fCL = 3MHz at VDD = 10V • Test Mode Allows Fast Test Sequence • Set and Reset Inputs • Capable of Driving Two Low Power TTL Loads, One Lower Power Schottky Load, or Two HTL Loads Over the Rated Temperature Range • 100% Tested for Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Standardized, Symmetrical Output Characteristics • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” December 1992 File Number 3345 Pinout CD4536BMS TOP VIEW 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 SET RESET IN 1 OUT 1 OUT 2 8-BYPASS VSS CLOCK INHIBIT VDD OSC INHIBIT DECODE OUT D C B A MONO IN BINARY SELECT Functional Diagram OSC 14 6 9 10 11 12 1 2 15 A B C D BINARY SELECT 8-BYPASS INHIBIT CLOCK INHIBIT SET RESET MONO IN 73 RS 4 5 OUT 1 OUT 2 RT 13 DECODE OUT IN 1 VSS = 8 VDD = 16 |
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