Datenblatt-Suchmaschine für elektronische Bauteile |
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CD4724BMS Datenblatt(PDF) 1 Page - Intersil Corporation |
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CD4724BMS Datenblatt(HTML) 1 Page - Intersil Corporation |
1 / 10 page 7-1267 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 CD4724BMS CMOS 8-Bit Addressable Latch Pinout CD4724BMS TOP VIEW Functional Diagram 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 A0 A1 A2 Q0 Q1 Q2 VSS Q3 VDD WRITE DISABLE DATA Q7 Q6 Q5 Q4 RESET DECODER 4 5 6 7 9 10 11 12 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 14 13 WRITE DISABLE DATA A0 A1 A2 RESET VDD = 16 VSS = 8 8 1 2 3 Features • High Voltage Type (20V Rating) • Serial Data Input • Active Parallel Output • Storage Register Capability • Master Clear • Can Function as Demultiplexer • Standardized Symmetrical Output Characteristics • 100% Tested for Quiescent Current at 20V • Maximum Input Current of 1 µA at 18V Over Full Pack- age Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • 5V, 10V and 15V Parametric Ratings • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” Applications • Multi-line Decoders • A/D Converters Description CD4724BMS 8-bit addressable latch is a serial-input, parallel- output storage register that can perform a variety of functions. Data are inputted to a particular bit in the latch when that bit is addressed (by means of inputs A0, A1, A2) and when WRITE DISABLE is at a low level. When WRITE DISABLE is high, data entry is inhibited; however, all 8 outputs can be continuously read independent of WRITE DISABLE and address inputs. A master RESET input is available, which resets all bits to a logic “0” level when RESET and WRITE DISABLE are at a high level. When RESET is at a high level, and WRITE DISABLE is at a low level, the latch acts as a 1-of-8 demultiplexer; the bit that is addressed has an active output which follows that data input, while all unaddressed bits are held to a logic “0” level. The CD4724BMS is supplied in these 16-lead outline pack- ages: Braze Seal DIP H4W Frit Seal DIP H1F Ceramic Flatpack H6W December 1992 File Number 3348 |
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