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AD9943KCPZ Datenblatt(PDF) 5 Page - Analog Devices

Teilenummer AD9943KCPZ
Bauteilbeschribung  Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors
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Hersteller  AD [Analog Devices]
Direct Link  http://www.analog.com
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AD9943KCPZ Datenblatt(HTML) 5 Page - Analog Devices

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Data Sheet
AD9943/AD9944
Parameter
Min
Typ
Max
Unit
Conditions
VOLTAGE REFERENCE
Reference Top Voltage (REFT)
2.0
V
Reference Bottom Voltage (REFB)
1.0
V
SYSTEM PERFORMANCE
Specifications include entire signal chain.
Gain Range
Low Gain (VGA Code = 0)
5.3
dB
Maximum Gain (VGA Code = 1023)
40
41.5
dB
Gain Accuracy
±1
dB
Peak Nonlinearity 500 mV Input Signal
0.1
%
12 dB gain applied.
Total Output Noise
0.9
LSB rms
AC grounded input, 6 dB gain applied.
Power Supply Rejection (PSR)
50
dB
Measured with step change on supply.
1
Input signal characteristics defined as follows:
TIMING SPECIFICATIONS
CL = 20 pF, fSAMP = 25 MHz. See CCD-mode timing in Figure 14 and Figure 15, and serial timing in Figure 10 and Figure 11.
Table 4.
Parameter
Symbol
Min
Typ
Max
Unit
SAMPLE CLOCKS
DATACLK, SHP, SHD Clock Period
tCONV
40
ns
DATACLK High/Low Pulse Width
tADC
16
20
ns
SHP Pulse Width
tSHP
10
ns
SHD Pulse Width
tSHD
10
ns
CLPOB Pulse Width1
tCOB
2
20
Pixels
SHP Rising Edge to SHD Falling Edge
tS1
10
ns
SHP Rising Edge to SHD Rising Edge
tS2
16
20
ns
Internal Clock Delay
tID
3.0
ns
DATA OUTPUTS
Output Delay
tOD
9.5
ns
Pipeline Delay
9
Cycles
SERIAL INTERFACE
Maximum SCK Frequency
fSCLK
10
MHz
SL to SCK Setup Time
tLS
10
ns
SCK to SL Hold Time
tLH
10
ns
SDATA Valid to SCK Rising Edge Setup
tDS
10
ns
SCK Falling Edge to SDATA Valid Hold
tDH
10
ns
1 Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
100mV TYP
OPTICAL BLACK PIXEL
500mV TYP
RESET TRANSIENT
1V TYP
INPUT SIGNAL RANGE
Rev. C | Page 5 of 20


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