Datenblatt-Suchmaschine für elektronische Bauteile |
|
ADF4193 Datenblatt(PDF) 4 Page - Analog Devices |
|
ADF4193 Datenblatt(HTML) 4 Page - Analog Devices |
4 / 32 page ADF4193 Data Sheet Rev. F | Page 4 of 32 Parameter B Version1 CVersion2 Unit Test Conditions/Comments SW1, SW2, and SW3 RON (SW1 and SW2) 65 65 Ω typ RON SW3 75 75 Ω typ NOISE CHARACTERISTICS Output 900 MHz4 −108 −108 dBc/Hz typ At 5 kHz offset and 26 MHz PFD frequency 1800 MHz5 −102 −102 dBc/Hz typ At 5 kHz offset and 13 MHz PFD frequency Phase Noise Normalized Phase Noise Floor (PNSYNTH)6 −216 −216 dBc/Hz typ At VCO output with dither off, PLL loop bandwidth = 500 kHz Normalized 1/f Noise (PN1_f)7 −110 −110 dBc/Hz typ Measured at 10 kHz offset, normalized to 1 GHz 1 Operating temperature range is from −40°C to +85°C. 2 Operating temperature range is from −40°C to +105°C 3 The prescaler value is chosen to ensure that the RF input is divided down to a frequency that is less than this value. 4 fREFIN = 26 MHz; fSTEP = 200 kHz; fRF = 900 MHz; loop bandwidth = 40 kHz. 5 fREFIN = 13 MHz; fSTEP = 200 kHz; fRF = 1800 MHz; loop bandwidth = 60 kHz. 6 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider value) and 10 log(fPFD). PNSYNTH = PNTOT − 10 log(fPFD) − 20 log(N). 7 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF, and at an offset frequency, f, is given by PN = P1_f+ 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL™. TIMING CHARACTERISTICS AVDD = DVDD = 3 V ± 10%, VP1, VP2 = 5 V ± 10%, VP3 = 5.35 V ± 5%, AGND = DGND = GND = 0 V, RSET = 2.4 kΩ, dBm referred to 50 Ω, TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter Limit (B Version)1 Limit (C Version) 2 Unit Test Conditions/Comments t1 10 10 ns min LE setup time t2 10 10 ns min DATA to CLOCK setup time t3 10 10 ns min DATA to CLOCK hold time t4 15 15 ns min CLOCK high duration t5 15 15 ns min CLOCK low duration t6 10 10 ns min CLOCK to LE setup time t7 15 15 ns min LE pulse width 1 Operating temperature is from −40°C to +85°C. 2 Operating temperature is from −40°C to +105°C. CLK DATA DB23 (MSB) DB22 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) LE LE t2 t4 t5 t3 t7 t6 t1 Figure 2. Timing Diagram |
Ähnliche Teilenummer - ADF4193_15 |
|
Ähnliche Beschreibung - ADF4193_15 |
|
|
Link URL |
Privatsphäre und Datenschutz |
ALLDATASHEETDE.COM |
War ALLDATASHEET hilfreich? [ DONATE ] |
Über Alldatasheet | Werbung | Kontakt | Privatsphäre und Datenschutz | Linktausch | Hersteller All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |