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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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ADSP-BF524C Datenblatt(PDF) 3 Page - Analog Devices |
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ADSP-BF524C Datenblatt(HTML) 3 Page - Analog Devices |
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3 / 36 page  ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C Rev. A | Page 3 of 36 | March 2010 GENERAL DESCRIPTION This document describes the differences between the ADSP-BF52xC and the ADSP-BF52x standard Blackfin ® prod- uct. Please refer to the published ADSP-BF52x data sheet for general description and specifications. This document only describes the differences from that data sheet. The ADSP-BF52xC processors add a low power, high quality stereo audio codec for portable digital audio applications with one set of stereo programmable gain amplifier (PGA) line inputs and one monaural microphone input. It features two 24- bit analog-to-digital converter (ADC) channels and two 24-bit digital-to-analog (DAC) converter channels. The codec can operate as a master or a slave. It supports various master clock frequencies, including 12 MHz or 24 MHz for USB devices; standard 256 × fS or 384 × fS based rates, such as 12.288 MHz and 24.576 MHz; and many common audio sam- pling rates, such as 96 kHz, 88.2 kHz, 48 kHz, 44.1 kHz, 32 kHz, 24 kHz, 22.05 kHz, 16 kHz, 12 kHz, 11.025 kHz, and 8 kHz. The codec can operate at power supplies as low as 1.8 V for the analog circuitry and as low as 1.8 V for the digital circuitry. The maximum voltage supply is 3.6 V for all supplies. The codec software-programmable stereo output options provide the programmer with many application possibilities because the device can be used as a headphone driver or as a speaker driver. Its volume control functions provide a large range of gain control of the audio signal. CODEC DESCRIPTION The ADSP-BF52xC codec contains a central clock source, called the codec master clock (CODEC_MCLK) that produces a refer- ence clock for all internal audio data processing and synch- ronization. When using an external clock source to drive the CODEC_MCLK pin, care should be taken to select a clock source with less than 50 ps of jitter. Without careful generation of the CODEC_MCLK signal, the digital audio quality will suffer. To enable the codec to generate the central reference clock in a system, connect a crystal oscillator between the XTI/ CODEC_MCLK input pin and the XTO output pin. Figure 1. Codec Block Diagram CODEC AVDD VMID AGND MICBIAS CSB CSDA CSCL CMODE CONTROL INTERFACE RLINEIN MICIN LLINEIN OSCPD OSC CLKIN DIVIDER CLKOUT DIVIDER DIGITAL AUDIO INTERFACE VOLUME VOLUME MIC BOOST MUTE MUTE MUTE MUTE MUX MUX ADC ADC DIGITAL FILTERS HPVDD HPGND RHPOUT ROUT LOUT LHPOUT HEADPHONE DRIVER HEADPHONE DRIVER VOLUME/ MUTE VOLUME/ MUTE MUTE ATTEN/ MUTE ATTEN/ MUTE MUTE DAC DAC MUTE MUTE Σ Σ XTO |
Ähnliche Teilenummer - ADSP-BF524C_15 |
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Ähnliche Beschreibung - ADSP-BF524C_15 |
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