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ADSP-BF527C Datenblatt(PDF) 11 Page - Analog Devices |
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ADSP-BF527C Datenblatt(HTML) 11 Page - Analog Devices |
11 / 36 page ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C Rev. A | Page 11 of 36 | March 2010 SOFTWARE CONTROL INTERFACE The software control interface provides access to the programmer-selectable control registers and can operate with a 2-wire (TWI) or 3-wire (SPI) interface, depending on the setting of the CMODE pin. If the CMODE pin is set to 0, the 2-wire interface is selected; if 1, the 3-wire interface is selected. Within each control register is a control data-word consisting of 16 bits, MSB first. Bit B15 to Bit B9 are the register map address, and Bit B8 to Bit B0 are register data for the associated register map. When 2-wire (TWI) mode is selected, CSDA generates the serial control data-word; CSCL clocks the serial data; and CSB deter- mines the TWI device address. If the CSB pin is set to 0, the address selected is 0011010; if 1, the address is 0011011. When 3-wire (SPI) mode is selected, CSDA generates the con- trol data-word, CSCL clocks the control data-word into the codec, and CSB latches in the control data-word. Figure 11. Codec SPI Serial Interface Figure 12. Codec TWI Serial Interface B15 B14 CSB CSCL CSDA B0 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 REGISTER MAP ADDRESS REGISTER DATA P 9 8 1 – 7 9 8 1 – 7 9 8 1 – 7 S CSDA CSCL START ADDR R/W ACK ACK SUBADDRESS ACK STOP DATA Figure 13. Codec TWI Write and Read Sequences WRITE SEQUENCE READ SEQUENCE SA1 A7 A0 A(S) A(S) S B15 B9 0 01 0P 0 ... A1 A7 A0 A(S) ... B0 B8 B7 A(M) A(M) ... B0 B7 P ... ... ... DEVICE ADDRESS DEVICE ADDRESS REGISTER ADDRESS SA1 A7 A0 A(S) A(S) A(S) B15 B9 B8 0 ... ... DEVICE ADDRESS REGISTER ADDRESS REGISTER DATA (SLAVE DRIVE) REGISTER DATA S/P = START/STOP BIT. A0 = I2C R/W BIT. A(S) = ACKNOWLEDGE BY SLAVE. A(M) = ACKNOWLEDGE BY MASTER. A(M) = ACKNOWLEDGE BY MASTER (INVERSION). |
Ähnliche Teilenummer - ADSP-BF527C_15 |
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Ähnliche Beschreibung - ADSP-BF527C_15 |
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