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LF3320 Datenblatt(PDF) 10 Page - LOGIC Devices Incorporated

Teilenummer LF3320
Bauteilbeschribung  Horizontal Digital Image Filter
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Hersteller  LODEV [LOGIC Devices Incorporated]
Direct Link  http://www.logicdevices.com
Logo LODEV - LOGIC Devices Incorporated

LF3320 Datenblatt(HTML) 10 Page - LOGIC Devices Incorporated

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DEVICES INCORPORATED
LF3320
Horizontal Digital Image Filter
2-10
08/16/2000–LDS.3320-N
Video Imaging Products
FIGURE 13.
I/D REGISTER DATA PATHS
ALU
AB
ALU
AB
COEF 7
COEF 6
ALU
AB
ALU
AB
COEF 7
COEF 6
Delay Stage N–1
ALU
AB
ALU
AB
COEF 6
EVEN-TAP MODE
ODD-TAP MODE
ODD-TAP INTERLEAVE MODE
2
COEF 7
2
Delay Stage N
FIGURE 12.
SYMMETRIC COEFFICIENT SET EXAMPLES
1
2
3
4
5
6
7
8
Even-Tap, Even-Symmetric
Coefficient Set
Odd-Tap, Even-Symmetric
Coefficient Set
1
2
3
4
5
6
7
8
Even-Tap, Odd-Symmetric
Coefficient Set
1
2
3
4
5
6
7
The ALUs can perform two operations:
A+B and B–A. Bit 0 of Configuration
Register 0 determines the operation of
the ALUs in Filter A.
Bit 0 of Configuration Register 2 deter-
mines the operation of the ALUs in Filter
B. A+B is used with
even-
symmetric coefficient sets. B–A is used
withodd-symmetriccoefficientsets.
Also, either the A or B operand may be
set to 0. Bits 1 and 2 of Configuration
Register 0 and Configuration Register 2
control the ALU inputs in
Filters A and B respectively. A+0 or B+0
are used with asymmetric coefficient
sets.
Interleave/DecimationRegisters
TheInterleave/DecimationRegisters(I/D
Registers)feedtheALUinputs. They
allow the device to filter up to sixteen data
sets interleaved into the same data stream
without having to separate the data sets.
The I/D Registers should be set to a length
equaltothenumberofdatasetsinter-
leavedtogether.
For example, if two data sets are inter-
leavedtogether,theI/DRegistersshould
be set to a length of two. Bits 1 through 4 of
ConfigurationRegister1andConfigura-
tionRegister3determinethelengthofthe
I/DRegistersinFilters A and Brespec-
tively.
The I/D Registers also facilitate using
decimationtoincreasethenumberoffilter
taps. Decimation by N is accomplished by
readingthefilter’soutputonceeveryN
clock cycles. The device supports decima-
tion up to 16:1. With no decimation, the
maximumnumberoffiltertapsissixteen.
WhendecimatingbyN,thenumberof
filtertapsbecomes16Nbecausethereare
N–1 clock cycles when the filter’s output is
not being read. The extra clock cycles are
usedtocalculatemorefiltertaps.
When decimating, the I/D Registers
should be set to a length equal to the
decimation factor. For example, when
performing a 4:1 decimation, the I/D
Registers should be set to a length of
four. When decimation is disabled or
when only one data set (non-interleaved
data) is fed into the device, the I/D
Registers should be set to a length of
one.


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