LF43881JC40 datasheet(1/11 Pages) LODEV

Teilenummer	LF43881JC40

Bauteilbeschribung	8 x 8-bit Digital Filter

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Hersteller	LODEV [LOGIC Devices Incorporated]

Direct Link	http://www.logicdevices.com

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DEVICES INCORPORATED

LF43881

8 x 8-bit Digital Filter

Video Imaging Products

08/16/2000–LDS.43881-J

1

u

u 25 MHz Maximum Sampling Rate

u

u 320 MHz Multiply-Accumulate Rate

u

u 8 Filter Cells

u

u 8-bit Unsigned or Two’s Complement

Data

u

u 8-bit Unsigned or Two’s Complement

Coefficients

u

u 26-bit Data Outputs

u

u Shift-and-Add Output Stage for

Combining Filter Outputs

u

u Expandable Data Size, Coefficient

Size, and Filter Length

u

u User-Selectable 2:1, 3:1, or 4:1

Decimation

u

u Replaces Harris HSP43881

u

u 84-pin PLCC, J-Lead

FEATURES

DESCRIPTION

LF43881

8 x 8-bit Digital Filter

DEVICES INCORPORATED

The LF43881 is a video-speed digital

filter that contains eight filter cells

(taps) cascaded internally and a shift-

and-add output stage. An 8 x 8

multiplier, three decimation registers,

and a 26-bit accumulator are con-

tained in each filter cell. The output

stage of the LF43881 contains a 26-bit

accumulator which can add the

contents of any filter stage to the

output stage accumulator shifted right

by 8 bits. 8-bit unsigned or two’s

complement format for data and

coefficients can be independently

selected.

Expanded coefficients and word sizes

can be processed by cascading mul-

tiple LF43881s to implement larger

filter lengths without affecting the

sample rate. By reducing the sample

rate, a single LF43881 can process

larger filter lengths by using multiple

passes. The sampling rate can range

from 0 to 40 MHz. Over 1000 taps

may be processed without overflows

due to the architecture of the device.

The output sample rate can be re-

duced to one-half, one-third, or one-

fourth the input sample rate by using

the three decimation registers con-

tained in every filter cell. Matrix

multiplication, N x N spatial correla-

tions/convolutions, and other 2-D

operations for image processing can

also be achieved using these registers.

LF43881 BLOCK DIAGRAM

FILTER

CELL 0

FILTER

CELL 1

8

FILTER

CELL 2

8

FILTER

CELL 3

8

FILTER

CELL 4

8

FILTER

CELL 5

8

FILTER

CELL 6

8

FILTER

CELL 7

8

26

8

MUX

5

DIN7-0

TCS

DIENB, CIENB,

ERASE, DCM1-0

TCCI

CIN7-0

ADR2-0

3

OUTPUT

STAGE

26

SHADD

SENBL

SENBH

SUM25-0

8

TCCO

COUT7-0

COENB

TO ALL REGISTERS

CLK

TO ALL CELLS

RESET

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