74LV4094_15 datasheet(6/21 Pages) PHILIPS

Teilenummer	74LV4094

Bauteilbeschribung	8-stage shift-and-store bus register

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74LV4094

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Product data sheet

Rev. 4 — 19 December 2011

6 of 21

NXP Semiconductors

74LV4094

8-stage shift-and-store bus register

8.

Limiting values

[1]

For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.

[2]

For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.

[3]

For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 C.

9.

Recommended operating conditions

[1]

The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V, but LV devices are guaranteed to function down to

VCC = 1.0 V (with input levels GND or VCC).

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

Parameter

Conditions

Min

Max

Unit

VCC

supply voltage

0.5

+7

V

IIK

input clamping current

VI < 0.5 V or VI >VCC +0.5 V

-

20

mA

IOK

output clamping current

VO < 0.5 V or VO >VCC +0.5 V

-

50

mA

IO

output current

VO = 0.5 V to (VCC +0.5 V)

-

25

mA

ICC

supply current

-

+50

mA

IGND

ground current

50

-

mA

Tstg

storage temperature

65

+150

C

Ptot

total power dissipation

Tamb = 40 C to +125 C

DIP16 package

[1] -

750

mW

SO16 package

[2] -

500

mW

(T)SSOP16 package

[3] -

500

mW

Table 5.

Recommended operating conditions

Voltages are referenced to GND (ground = 0 V).

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VCC

supply voltage

[1] 1.03.3

3.6V

VI

input voltage

0

-

VCC

V

VO

output voltage

0

-

VCC

V

Tamb

ambient temperature

40

+25

+125

C

t/V

input transition rise and fall rate

VCC = 1.0 V to 2.0 V

-

500

ns/V

VCC = 2.0 V to 2.7 V

-

200

ns/V

VCC = 2.7 V to 3.6 V

-

100

ns/V

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