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STC5428 Datenblatt(PDF) 6 Page - Connor-Winfield Corporation |
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STC5428 Datenblatt(HTML) 6 Page - Connor-Winfield Corporation |
6 / 66 page Page 6 of 66 Rev: 0.2 Date: April 3, 2014 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice STC5428 Synchronous Clock for SETS DATASHEET Preliminary STC5428 Pin Description All I/O is LVCMOS, except for CLK1 and CLK2 are LVPECL/LVDS. REF11 and REF12 are LVPECL/LVDS. Table 1: Pin Description Pin Name Pin # I/O Description AGND 4 Analog ground AVCC 5 3.3V analog power input VCC 10, 12, 20, 25, 39, 43, 48, 49, 55, 60, 61 3.3V digital power input GND 1, 11, 14, 15, 44, 57, 63, 67 Digital ground TRST 2 I JTAG boundary scan reset, active low TCK 8 I JTAG boundary scan clock TMS 6 I JTAG boundary scan mode selection TDI 17 I JTAG boundary scan data input TDO 16 O JTAG boundary scan data output RST 51 I Active low to reset the chip MCLK 9 I Master clock input (TCXO or OCXO) EVENT_INTR 7 O Event interrupt MC/SL 68 I Hardware select for T0 master/slave mode selection EX_SYNC 30 I Frame Sync signal REF1 32 I Reference input 1 REF2 33 I Reference input 2 REF3 34 I Reference input 3 REF4 35 I Reference input 4 REF5 36 I Reference input 5 REF6 37 I Reference input 6 REF7 38 I Reference input 7 REF8 40 I Reference input 8 REF9 41 I Reference input 9 REF10 42 I Reference input 10 REF11_P 26 I Differential reference input 11 positive (LVPECL/LVDS) REF11_N 27 I Differential reference input 11 negative (LVPECL/LVDS) REF12_P 28 I Differential reference input 12 positive (LVPECL/LVDS) |
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