 |
Datenblatt-Suchmaschine für elektronische Bauteile |
|
|
Datenblatt-Suchmaschine für elektronische Bauteile |
|
STC5455 Datenblatt(PDF) 9 Page - Connor-Winfield Corporation |
|
||||||||||||||||||||||||||||||
STC5455 Datenblatt(HTML) 9 Page - Connor-Winfield Corporation |
|
|
9 / 56 page  Page 9 of 56 TM121 Rev:P1.3 Date: October 24, 2011 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice STC5455 Synchronous Clock for SETS Data sheet Preliminary Note 1: Timing generator T0 and T4 share register 0x20 ~ 0x3F. Register 0x1F selects between T0 and T4 for the sharing registers 0x20 ~0x3F. 0x2D Short_Term_Accu_History 31-0 R Short term Accumulated History 0x2E 0x2F 0x30 0x31 User_Specified_History 31-0 R/W User programmed holdover history 0x32 0x33 0x34 0x35 History_Ramp 7-0 R/W Control long term history and short term history accumulation band- width and the locking stage’s frequency ramp control 0x36 Ref_Priority_Table 19-0 R/W REF1-5 selection priority 0x37 0x38 0x3C PLL_Status 7-0 R PLL status: SYNC, LOS, LOL, OOP, SAP, FEE, DHT, HHA 0x3D Holdover_Accu_Flush 0 W Flush/reset the long-term history and the device holdover history 0x3E PLL_Event_Out 7-0 R/W PLL event out (Reserved) 0x3F PLL_Event_In 7-0 R/W PLL event in: Relock 0x40 EX_SYNC_Edge_Config 2-0 R/W Select framing edge (falling or rising edge) for EX_SYNC1/2/3 0x42 Frame_Phase_Align 19-0 R/W Selects frame reference input and sampling edge on selected refer- ence for frame alignment. (T0 timing generator only) 0x43 0x44 0x4A Synth_Index_Select 3-0 R/W Select a synthesizer to access registers Synth_Freq_Value and Synth_Skew_Adj 0x4B Synth_Freq_Value 17-0 R/W Selects synthesizer frequency value from 1MHz to 156.25MHz, in 1kHz steps, based on which synthesizer index is selected at the reg- ister Synth_Index_Select 0x4C 0x4D 0x4E Synth_Skew_Adj 11-0 R/W Adjust phase skew for the synthesizer with the index selected at register Synth_Index_Select 0x4F 0x50 CLK1_Signal_Level 0 R/W Select the signal level (LVDS or LVPECL) for clock outputs CLK1 0x51 CLK1_Sel 1-0 R/W Select synthesizer or enable tri-state for CLK1 0x52 CLK2_Sel 1-0 R/W Select synthesizer or enable tri-state for CLK2 0x59 Frame8K_Sel 6-0 R/W 8kHz frame pulse clock output duty cycle selection, signal inversion 0x5A Frame2K_Sel 6-0 R/W 2kHz frame pulse clock output duty cycle selection, signal inversion 0x5B Ref__Acceptable_Freq 14-0 R/W Select integer N for manually acceptable frequency at Nx8kHz; Enable auto detection of reference input frequency 0x5C 0x5D Frame_Mux 1-0 R/W Select one of frame signal (Frame8K, Frame2K) and forward it to CLK2 selection 0x70 Field_Upgrade_Status 2-0 R Indicates the status of field upgrade process 0x71 Field_Upgrade_Data 7-0 R/W Load 7600 bytes of firmware configuration data 0x72 Field_Upgrade_Count 12-0 R Count byte numbers that have been loaded 0x73 0x74 Field_Upgrade_Start 7-0 W Write three values consecutively to start the field upgrade process 0x7F MCLK_Freq_Reset 7-0 R/W Select the frequency of the external oscillator Table 2: Register Map Addr Reg Name Bits Type Description |
Ähnliche Teilenummer - STC5455 |
|
Ähnliche Beschreibung - STC5455 |
|
|
Link URL |
| Privatsphäre und Datenschutz |
| ALLDATASHEETDE.COM |
| War ALLDATASHEET hilfreich? [ DONATE ] |
Über Alldatasheet | Werbung | Kontakt | Privatsphäre und Datenschutz | Linktausch | Hersteller All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
German ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
