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DAC5670-SP Datenblatt(PDF) 11 Page - Texas Instruments

Teilenummer DAC5670-SP
Bauteilbeschribung  DAC5670-SP 14-Bit 2.4-GSPS Digital-to-Analog Converter (DAC)
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Hersteller  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

DAC5670-SP Datenblatt(HTML) 11 Page - Texas Instruments

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DACLK_P/N
DACCLK/2 internal
toDAC5670
DLYCLK_P/N
DTCLK_P/N
DA_P/N[13:0]
DB_P/N[13:0]
internal data to
the DAC core in
NORMAL mode
a0
a1
a2
a3
b3
b2
b1
b0
a0
b0
a1
b1
This internal DACCLK/2 is used to clock the input data DA and DB into theDAC5670
DLYCLK is DACCLK/4 delayed by the DAC5670 DLL to be used as the DDR clock for the data source digital chip
DTCLK is a toggling bit, aligned with DA and DB data from chip, used by the DAC5670 DLL feedback path
7 DACCLKs
Pipeline Delay
DAC5670-SP
www.ti.com
SGLS386F – JANUARY 2009 – REVISED OCTOBER 2014
7.7 Digital Electrical Characteristics
TC,MIN = –55°C to TC,MAX = 125°C, typical values at 25°C, AVDD = 3 to 3.6 V, IoutFS = 20 mA (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
CMOS INTERFACE (SLEEP, RESTART, INV_CLK, NORMAL, A_ONLY, A_ONLY_INV, A_ONLY_ZS)
IIH
High-level input current
0.2
10
μA
IIL
Low-level input current
–10
–0.2
μA
Input capacitance
2.5(2)
pF
DIFFERENTIAL DATA INTERFACE (DA_P[13:0], DA_N[13:0], DB_P[13:0], DB_N[13:0], DTCLK_P, DTCLK_N)
ZT
Internal termination impedance
80
100
125
Ci
Input capacitance
2.6(2)
pF
(1)
Typicals are characterization values at 25°C and AVDD = 3.3 V. These parameters are characterized, but not production tested.
(2)
Specified by design.
7.8 Timing Requirements
MIN
TYP
MAX
UNIT
DIFFERENTIAL DATA INTERFACE (DA_P[13:0], DA_N[13:0], DB_P[13:0], DB_N[13:0] EXTERNAL TIMING WITH DLL IN RESTART)
(See Figure 2)
RESTART = 1, DLYCLK 20-pF load
tsetup
Data setup to DLYCLK(1)
4.75
nS
See Figure 2
RESTART = 1, DLYCLK 20-pF load
thold
Data hold to DLYCLK (1)
–3.5
nS
See Figure 2
DLL (See Figure 15)
NegD
DLL min negative delay
RESTART = 0
150
ps
PosD
DLL min positive delay
RESTART = 0
600
ps
CLK/4 internal setup + hold
tvalid
160
ps
width
Fdac
RESTART = 0
1
2.4
GHz
(1)
Tested using SNR as pass/fail criteria.
Figure 1. DLL Input Loop Functional Timing
Copyright © 2009–2014, Texas Instruments Incorporated
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