7

ter capacitor. Ceramic bypass capacitors (0.1µF) connected

filtering. This provides a low impedance path for filtering

the high frequency noise. All high current loops should be

kept as short as possible using heavy copper runs. The

error amp compensation circuitry and the converter out-

put voltage-divider should be located close to the IC and

as far as possible from the power switch and other noise

generating components.

Operating Description: continued

SYNC

Latch 1

“Set” Input

Latch 1

“Reset” Input

Latch 2

“Set” Input

Latch 2

“Reset” Input

0V

Timing Diagram

+

-

+

+

+

+

-

1

Reference

Regulator

UVLO

3.4V

8.4V

2.5V

R

R

20k

Ω

Sync

1mA

2R

1.0V

250

µA

R

2R

Error

Amp 2

2

Gnd

Pwr Gnd

R

1.0V

Current Sense

Comparator 2

Current Sense

Comparator 1

R

S

R

S

R

PWM

Latch 2

PWM

Latch 1

VIN

Q1

Q2

RSense1

RSense2

-

+

-

Error

Amp 1

5.0V

Q

Oscillator

Internal

Bias

CF1 +

L1

D1

L2

D2

+

+

CF2

1

2

3

4

2

Dual Boost Regulator

UVLO

+

Q

+

-

+

-

+

-

+

-

1mA

Typical Application Diagram