Datenblatt-Suchmaschine für elektronische Bauteile |
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TMP275 Datenblatt(PDF) 9 Page - Texas Instruments |
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TMP275 Datenblatt(HTML) 9 Page - Texas Instruments |
9 / 33 page TMP275 www.ti.com SBOS363E – JUNE 2006 – REVISED NOVEMBER 2015 7.3.2 Serial Interface The TMP275 operates only as slave devices on the SMBus, Two-Wire, and I2C interface-compatible bus. Connections to the bus are made through the open-drain I/O lines SDA and SCL. The SDA and SCL pins feature integrated spike suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. The TMP275 supports the transmission protocol for fast (up to 400 kHz) and high-speed (up to 2.38 MHz) modes. All data bytes are transmitted MSB first. 7.3.3 Bus Overview The device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. To address a specific device, a START condition is initiated, indicated by pulling the data-line (SDA) from a HIGH to LOW logic level while SCL is HIGH. All slaves on the bus shift in the slave address byte, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed responds to the master by generating an Acknowledge and pulling SDA LOW. Data transfer is then initiated and sent over eight clock pulses followed by an Acknowledge Bit. During data transfer SDA must remain stable while SCL is HIGH, as any change in SDA while SCL is HIGH will be interpreted as a control signal. Once all data has been transferred, the master generates a STOP condition indicated by pulling SDA from LOW to HIGH, while SCL is HIGH. 7.3.4 Serial Bus Address To communicate with the TMP275, the master must first address slave devices through a slave address byte. The slave address byte consists of 7 address bits, and a direction bit indicating the intent of executing a read or write operation. The TMP275 features three address pins, allowing up to eight devices to be connected per bus. Pin logic levels are described in Table 2. The address pins of the TMP275 are read after reset, at start of communication, or in response to a Two-Wire address acquire request. Following reading the state of the pins the address is latched to minimize power dissipation associated with detection. Table 2. Address Pins and Slave Addresses for the TMP275 A2 A1 A0 SLAVE ADDRESS 0 0 0 1001000 0 0 1 1001001 0 1 0 1001010 0 1 1 1001011 1 0 0 1001100 1 0 1 1001101 1 1 0 1001110 1 1 1 1001111 7.3.4.1 Writing and Reading to the TMP275 Accessing a particular register on the TMP275 is accomplished by writing the appropriate value to the Pointer Register. The value for the Pointer Register is the first byte transferred after the slave address byte with the R/W bit LOW. Every write operation to the TMP275 requires a value for the Pointer Register. (see Figure 8.) Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: TMP275 |
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Ähnliche Beschreibung - TMP275_15 |
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