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SM8702AM Datenblatt(PDF) 8 Page - Nippon Precision Circuits Inc |
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SM8702AM Datenblatt(HTML) 8 Page - Nippon Precision Circuits Inc |
8 / 16 page SM8702AM NIPPON PRECISION CIRCUITS—8 PCI clock characteristics Ta = 0 to 70°C, VDD = 3.3V ± 5%, VSS = 0V, fX’tal = 14.318MHz, CL = 30pF unless otherwise noted. SDRAM clock characteristics Ta = 0 to 70°C, VDD = VDDL = 3.3V ± 5%, VSS = 0V, fX’tal = 14.318MHz, CL = 30pF unless otherwise noted. P arameter Symbol Condition Rating Unit min typ m a x Output clock rise time1 1. Design maximu m values, not 100% guaranteed. tr V OL = 0.8V → VOH = 2.4V transition time – – 2.0 ns Output clock fall time1 tf V OH = 2.4V → VOL = 0.8V transition time – – 2.0 ns Duty cycle Dt V T = 1.5V 4 5 5 0 5 5 % Output clock jitter1 tjc V T = 1.5V, rising edge Cycle-to-cycle jitter – – 2 5 0 ps Output clock skew 1 tskw V T = 1.5V, rising edge Between PCI clocks: PCICLK_F and PCICLK[0:4] – – 250 ps CPU/PCI clock skew 2 2. CPUCLK and PCICLK r ising edges, V T-CPUCLK = 1.25V (VDDL = 2.5V)/1.5V (VDDL = 3.3V), V T-PCICLK = 1.5V skew measurement. thpsk V T-CPUCLK = 1.25/1.5V, V T-PCICLK = 1.5V, rising edges Between CPU and PCI clocks: CPUCLK[0:1] and PCICLK_F/PCICLK[0:4] 1.0 2.2 4.0 ns Clock frequency stabilize time1 tstb Cold star t Supply ON (VDD = 3.3V) until clock reaches specified frequency ––3 m s Output impedance3 3. Design estimate values, not 100% guaranteed. Z O V O = 0.5VDD 1 0–6 0 Ω P arameter Symbol Condition Rating Unit min typ m a x Output clock rise time1 1. Design maximu m values, not 100% guaranteed. tr V OL = 0.8V → VOH = 2.4V transition time – – 2.0 ns Output clock fall time1 tf V OH = 2.4V → VOL = 0.8V transition time – – 2.0 ns Duty cycle1 Dt V T = 1.5V, BUFFERIN input clock signal rise and fall time rate ≥ 1V/ns 3.3V BUFFERIN input clock signal logic level 40 50 60 % Output clock skew 1 tskw V T = 1.5V, rising edge, B UFFERIN input clock signal rise and fall time rate ≥ 1V/ns Between SDRAM clocks: SDRAM[0:13] – 200 600 ps Input to output propagation delay2,3 2. B UFFERIN and SDRAM r ising edges, V T-BUFFERIN = 1.5V (logic level = 3.3V), V T-SDRAM = 1.5V delay measurement. tpd V T-BUFFERIN = 1.5V, V T-SDRAM = 1.5V, rising edges, BUFFERIN input clock signal rise and fall time rate ≥ 1V/ns Between BUFFERIN and SDRAM[0:13] – 5.5 7.0 ns Output impedance3 3. Design estimate values, not 100% guaranteed. Z O V O = 0.5VDD 1 0–6 0 Ω |
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