Rev. 1.1 1/13

Copyright © 2013 by Silicon Laboratories

Si5355

Si5355

Features

Applications

Description

The Si5355 is a highly flexible clock generator capable of synthesizing four

completely non-integer related frequencies up to 200 MHz. The device has four

banks of outputs with each bank supporting two CMOS outputs at the same

frequency. Using Silicon Laboratories' patented MultiSynth fractional divider

technology, all outputs are guaranteed to have 0 ppm frequency synthesis error

regardless of configuration, enabling the replacement of multiple clock ICs and

crystal oscillators with a single device. Through a flexible web configuration utility

called ClockBuilder™ (www.silabs.com/ClockBuilder), factory-customized pin-

controlled Si5355 devices are available in two weeks without minimum order

quantity restrictions. The Si5355 supports up to three independent, pin-selectable

device configurations, enabling one device to replace three separate clock ICs.

Functional Block Diagram



Generates any frequency from 1 to

200 MHz on each of the 4 output banks



Eight CMOS clock outputs



Guaranteed 0 ppm frequency synthesis

error for any combination of frequencies



25 or 27 MHz xtal or 5–200 MHz input clk



Five programmable control pins (output

enable, frequency select, reset)



Separate OEB pins to disable individual

banks or all outputs



Loss of signal output



Low 50 ps (typ) pk-pk period jitter



Phase jitter: 2 ps rms 12 kHz–20 MHz



Excellent PSRR performance

eliminates need for external power

supply filtering



Low power: 45 mA (core)



Core VDD: 1.8, 2.5, or 3.3 V



Separate VDDO for each bank of

outputs: 1.8, 2.5, or 3.3 V



Small size: 4x4 mm 24-QFN



Industrial temperature range:

–40 to +85 °C



Custom versions available using

ClockBuilder™ web utility



Samples available in 2 weeks



Printers



Audio/video



Networking



Communications



Storage



Switches/routers



Computing



Servers



OC-3/OC-12 line cards

Ordering Information:

See page 17.

Pin Assignments

XA

CLK5

CLK4

VDDOC

VDDOB

CLK3

CLK2

GND

GND

XB

P1

CLKIN

P4

P5

Top View

1

6

5

4

3

2

712

11

10

9

8

18

13

14

15

16

17

24

19

20

21

22

23

XA

CLK5

CLK4

VDDOC

VDDOB

CLK3

CLK2

GND

GND

XB

P1

CLKIN

P4

P5

Top View

1

6

5

4

3

2

712

11

10

9

8

18

13

14

15

16

17

24

19

20

21

22

23