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AD5721RBCPZ-RL7 Datenblatt(PDF) 11 Page - Analog Devices |
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AD5721RBCPZ-RL7 Datenblatt(HTML) 11 Page - Analog Devices |
11 / 35 page Data Sheet AD5761R/AD5721R Rev. A | Page 11 of 35 12 11 10 1 3 4 9 2 AD5761R/ AD5721R TOP VIEW (Not to Scale) NOTES 1. DNC = DO NOT CONNECT. 2. THE EXPOSED PAD MUST BE MECHANICALLY CONNECTED TO THE PCB COPPER PLANE FOR OPTIMAL THERMAL PERFORMANCE. THE EXPOSED PAD CAN BE LEFT ELECTRICALLY FLOATING. RESET VREFIN/VREFOUT AGND VSS SCLK SYNC SDI LDAC Figure 6. 16-Lead LFCSP Pin Configuration Table 6. 16-Lead LFCSP Pin Function Descriptions Pin No. Mnemonic Description 1 RESET Active Low Reset Input. Asserting this pin returns the AD5761R/AD5721R to their default power-on status where the output is clamped to ground and the output buffer is powered down. This pin can be left floating because there is an internal pull-up resistor. 2 VREFIN/VREFOUT Internal Reference Voltage Output and External Reference Voltage Input. For specified performance, VREFIN/VREFOUT = 2.5 V. Connect a 10 nF capacitor with the internal reference to minimize the noise. 3 AGND Ground Reference Pin for Analog Circuitry. 4 VSS Negative Analog Supply Connection. A voltage in the range of −16.5 V to 0 V can be connected to this pin. For unipolar output ranges, connect this pin to 0 V. VSS must be decoupled to AGND. 5 VOUT Analog Output Voltage of the DAC. The output amplifier is capable of directly driving a 2 kΩ, 1 nF load. 6 VDD Positive Analog Supply Connection. A voltage in the range of 4.75 V to 30 V can be connected to this pin for unipolar output ranges. Bipolar output ranges accept a voltage in the range of 4.75 V to 16.5 V. VDD must be decoupled to AGND. 7 DNC Do Not Connect. Do not connect to this pin. 8 SDO Serial Data Output. This pin clocks data from the serial register in daisy-chain or readback mode. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK. 9 LDAC Load DAC. This logic input updates the DAC register and, consequently, the analog output. When tied permanently low, the DAC register is updated when the input register is updated. If LDAC is held high during the write to the input register, the DAC output register is not updated, and the DAC output update is held off until the falling edge of LDAC. This pin can be left floating because there is an internal pull-up resistor. 10 SDI Serial Data Input. Data must be valid on the falling edge of SCLK. 11 SYNC Active Low Synchronization Input. This pin is the frame synchronization signal for the serial interface. While SYNC is low, data is transferred in on the falling edge of SCLK. Data is latched on the rising edge of SYNC. 12 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. This pin operates at clock speeds of up to 50 MHz. 13 DVCC Digital Supply. The voltage range is from 1.7 V to 5.5 V. The applied voltage sets the voltage at which the digital interface operates. 14 DGND Digital Ground. 15 ALERT Active Low Alert. This pin is asserted low when the die temperature exceeds approximately 150°C, or when an output short circuit or a brownout occurs. This pin is also asserted low during power-up, a full software reset, or a hardware reset, for which a write to the control register asserts the pin high. 16 CLEAR Falling Edge Clear Input. Asserting this pin sets the DAC register to zero scale, midscale, or full-scale code (user selectable) and updates the DAC output. This pin can be left floating because there is an internal pull-up resistor. EPAD Exposed Pad. The exposed pad must be mechanically connected to the PCB copper plane for optimal thermal performance. The exposed pad can be left electrically floating. |
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Ähnliche Beschreibung - AD5721RBCPZ-RL7 |
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