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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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54ACT825L Datenblatt(PDF) 2 Page - National Semiconductor (TI) |
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54ACT825L Datenblatt(HTML) 2 Page - National Semiconductor (TI) |
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2 / 8 page  Connection Diagrams Functional Description The ’ACT825 consists of eight D-type edge-triggered flip-flops. These devices have TRI-STATE® outputs for bus systems, organized in a broadside pinning. In addition to the clock and output enable pins, the buffered clock (CP) and buffered Output Enable (OE) are common to all flip-flops. The flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH CP transition. With OE 1,OE2 and OE3 LOW, the contents of the flip-flops are available at the outputs. When one of OE 1,OE2 or OE3 is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. The ’ACT825 has Clear (CLR) and Clock Enable (EN) pins. These pins are ideal for parity bus interfacing in high performance systems. When CLR is LOW and OE is LOW, the outputs are LOW. When CLR is HIGH, data can be entered into the flip-flops. When EN is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When EN is HIGH, the outputs do not change state, regardless of the data or clock input transitions. Function Table Inputs Internal Output Function OE CLR EN CP D n QO HX L N L L Z High-Z HX L N H H Z High-Z H L X X X L Z Clear L L X X X L L Clear H H H X X NC Z Hold L H H X X NC NC Hold HH L N L L Z Load HH L N H H Z Load LHL N L L L Load LHL N H H H Load H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance N = LOW-to-HIGH Transition NC = No Change Pin Assignment for DIP and Flatpak DS100254-2 Pin Assignment for LCC DS100254-4 www.national.com 2 |
Ähnliche Teilenummer - 54ACT825L |
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Ähnliche Beschreibung - 54ACT825L |
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