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SI53119 Datenblatt(PDF) 7 Page - Silicon Laboratories

Teilenummer SI53119
Bauteilbeschribung  19-OUTPUT PCIE GEN 3 BUFFER
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Hersteller  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
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Si53119
Rev. 1.1
7
Table 5. Output Skew, PLL Bandwidth and Peaking
TA = 0–70 °C; supply voltage VDD =3.3 V ±5%
Parameter
Test Condition
Min
TYP
Max
Unit
CLK_IN, DIF[x:0]
Input-to-Output Delay in PLL Mode
Nominal Value1,2,3,4
–100
18
100
ps
CLK_IN, DIF[x:0]
Input-to-Output Delay in Bypass Mode
Nominal Value2,4,5
2.5
3.6
4.5
ns
CLK_IN, DIF[x:0]
Input-to-Output Delay Variation in PLL mode
Over Voltage and Temperature2,4,5
–50
20
50
ps
CLK_IN, DIF[x:0]
Input-to-Output Delay Variation in Bypass Mode
Over Voltage and Temperature2,4,5
–250
250
ps
DIF[11:0]
Output-to-Output Skew across all 19 Outputs
(Common to Bypass and PLL Mode)1,2,3,4,5
0
20
50
ps
PLL Jitter Peaking
(HBW_BYPASS_LBW =0)6
0.4
2.0
dB
PLL Jitter Peaking
(HBW_BYPASS_LBW =1)6
—0.1
2.5
dB
PLL Bandwidth
(HBW_BYPASS_LBW =0)7
—0.7
1.4
MHz
PLL Bandwidth
(HBW_BYPASS_LBW =1)7
—2
4
MHz
Notes:
1.
Measured into fixed 2 pF load cap. Input-to-output skew is measured at the first output edge following the
corresponding input.
2.
Measured from differential cross-point to differential cross-point.
3.
This parameter is deterministic for a given device.
4.
Measured with scope averaging on to find mean value.
5.
All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created
by it.
6.
Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL
jitter peaking.
7.
Measured at 3 db down or half power point.


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