Datenblatt-Suchmaschine für elektronische Bauteile |
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SI53323 Datenblatt(PDF) 1 Page - Silicon Laboratories |
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SI53323 Datenblatt(HTML) 1 Page - Silicon Laboratories |
1 / 23 page Rev. 1.0 7/15 Copyright © 2015 by Silicon Laboratories Si53323 Si53323 1:4 L OW-J ITTER LV PECL C LOCK B UFFER WITH 2:1 I NPUT M UX Features Applications Description The Si53323 is an ultra-low-jitter four-output LVPECL buffer. The Si53323 features a 2:1 input mux, making it ideal for redundant clocking applications. Utilizing Silicon Laboratories’ advanced fan-out clock technology, the Si53323 guarantees low additive jitter, low skew, and low propagation delay variability from dc to 1250 MHz. The Si53323 features minimal cross-talk and excellent supply noise rejection, simplifying low-jitter clock distribution in noisy environments. Functional Block Diagram 4 LVPECL outputs Ultra-low additive jitter: 55 fs rms Wide frequency range: dc to 1250 MHz 2:1 input mux Universal input stage accepts differential or LVCMOS clock VDD: 2.5 / 3.3 V Small size: 16-QFN (3 mm x 3mm) RoHS compliant, Pb-free Industrial temperature range: –40 to +85 °C High-speed clock distribution Ethernet switch/router Optical Transport Network (OTN) SONET/SDH PCI Express Gen 1/2/3 Storage Telecom Industrial Servers Backplane clock distribution Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 VDD Power Supply Filtering CLK0 CLK0 CLK1 CLK1 CLK_SEL Switching Logic Patents pending Ordering Information: See page 18. Pin Assignments EXPOSED GND PAD 9 11 10 12 4 2 3 1 CLK_SEL CLK1 Q1 Q1 Q0 Q0 GND CLK1 |
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Ähnliche Beschreibung - SI53323 |
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