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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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CDCL1810 Datenblatt(PDF) 7 Page - Texas Instruments |
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CDCL1810 Datenblatt(HTML) 7 Page - Texas Instruments |
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7 / 33 page  CDCL1810 www.ti.com SLLS781D – FEBRUARY 2007 – REVISED NOVEMBER 2014 DC Electrical Characteristics (continued) Over recommended operating conditions (unless otherwise noted). TEST CONDITIONS MIN TYP MAX UNIT IIL,CMOS Low level CMOS input current VDD = VDD,max, VIL = 0.0 V –120 μA IIH,CMOS High level CMOS input current VDD = VDD,max, VIH = 1.9 V 65 μA Low level CMOS output voltage for the VOL,SDA Sink current = 3 mA 0 0.2VDD V SDA pin IOL,CMOS Low level CMOS output current 8 mA 8.6 AC Electrical Characteristics Over recommended operating conditions (unless otherwise noted). TEST CONDITIONS MIN TYP MAX UNIT ZD,IN Differential input impedance for the LVDS input terminals 90 132 Ω VCM,IN Common-mode voltage, LVDS input 1125 1200 1375 mV VS,IN Single-ended LVDS input voltage swing 100 600 mVPP VD,IN Differential LVDS input voltage swing 200 1200 mVPP tR,OUT, Output signal rise/fall time 20%–80% 100 ps tF,OUT VDD – VDD – VDD – VCM,OUT Common-mode voltage, CML outputs V 0.31 0.23 0.19 VS,OUT Single-ended CML output voltage swing ac-coupled 180 230 280 mVPP measured in a 50- Ω scope; The CML output VD,OUT Differential CML output voltage swing 360 460 560 mVPP incorporates 50- Ω resistors to VDD FIN Clock input frequency 650 MHz FOUT Clock output frequency 650 MHz 10Hz–1MHz offset 180 fs RMS FIN = 30.72MHz, FOUT = 30.72MHz 1MHz–5MHz offset 348 fs RMS VD,IN = 200mVPP 12kHz–5MHz offset 388 fs RMS 10Hz–1MHz offset 175 fs RMS FIN = 30.72MHz, FOUT = 30.72MHz 1MHz–5MHz offset 347 fs RMS VD,IN = 1200mVPP 12kHz–5MHz offset 388 fs RMS Additive clock output jitter JOUT 10Hz–1MHz offset 41 fs RMS FIN = 650MHz, FOUT = 650MHz 1MHz–20MHz offset 36 fs RMS VD,IN = 200mVPP 12kHz–20MHz offset 42 fs RMS 10Hz–1MHz offset 48 fs RMS FIN = 650MHz, FOUT = 650MHz 1MHz–20MHz offset 33 fs RMS VD,IN = 1200mVPP 12kHz–20MHz offset 39 fs RMS FIN = 30.72MHz, TP Input-to-output delay FOUT = 30.72MHz 0.7 ns YP[9:0] outputs FIN = 30.72MHz, FOUT = 30.72MHz TSOUT Clock output skew –64 64 ps YP[9:0] outputs relative to YP[0] Copyright © 2007–2014, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: CDCL1810 |
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