V

DD

CLKN

CLKP

YN[4:0]

YP[4:0]

YN[9:5]

YP[9:5]

SDA/SCL

See Note 1

Divider Setting

CML

CML

SDA/SCL

V

SS

LVDS

CML

CML

Divider

P0

Divider

P1

Control

SDA/SCL

Differential

LVDSInput

Upto650MHz

5Differential

CMLOutputs

Upto650MHz

5Differential

CMLOutputs

Upto650MHz

DIVIDER

DIVIDER

CDCL1810

SLLS781D – FEBRUARY 2007 – REVISED NOVEMBER 2014

www.ti.com

9 Detailed Description

9.1 Overview

The CDCL1810 is a high-performance 10 output clock distributor. The device operates form a single 1.8-V

supply. The outputs are grouped in to banks of 5 outputs each with independent frequency division ratios.

9.2 Functional Block Diagrams

Figure 4. SDA/SCL Interface

Note 1: Outputs can be disabled to floating. When outputs are left floating, internal 50

YN and YP to VDD.

10

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