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SL23EP09NZSC-1HT Datenblatt(PDF) 9 Page - Silicon Laboratories

Teilenummer SL23EP09NZSC-1HT
Bauteilbeschribung  Low Jitter and Skew DC to 220 MHz Clock Buffer
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Hersteller  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

SL23EP09NZSC-1HT Datenblatt(HTML) 9 Page - Silicon Laboratories

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Rev 2.2, May 6, 2008
Page 9 of 11
SL23EP09NZ
External Components & Design Considerations
Typical Application Schematic
SL23EP09NZ
0.1
μF
BUF_IN
OUTPUT2
GND
VDD
1
4,8,13
5,9,12
16
3
2
CL
OUTPUT1
CL
CL
OUTPUT9
Comments and Recommendations
Decoupling Capacitor:
A decoupling capacitor of 0.1μF must be used between all VDD and VSS pins. Place the
capacitor on the component side of the PCB as close to the VDD pin as possible. The PCB trace to the VDD pin and
to the GND via should be kept as short as possible. Do not use vias between the decoupling capacitor and the VDD
pin.
Series Termination Resistor: A series termination resistor is recommended if the distance between the output
clocks and the load is over 1 ½ inch. Place the series termination resistors as close to the clock outputs as possible.


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