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SL18861 Datenblatt(PDF) 1 Page - Silicon Laboratories

Teilenummer SL18861
Bauteilbeschribung  3-Channel Clock Distribution Buffer
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Hersteller  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

SL18861 Datenblatt(HTML) 1 Page - Silicon Laboratories

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Rev 1.2, December 21 , 2010
Page 1 of 12
2400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
www.silabs.com
SL18861DI
Key Features
• Low current consumption:
- 2.7mA-typ (VDD=1.8V, CL=0)
• 1.70V to 3.65V power supply operation
• 10MHz to 52MHz CLKIN range
• Supports LVCMOS or Sine Inputs
• Supports 3 single-ended LVCMOS square wave or
clipped sine wave outputs
• OE1/2/3 functions for each CLKOUT1/2/3 outputs
• OE_OSC control pin to enable external TCXO/XO
• Ultra-Low phase noise
• Ultra low standby current
• 10-pin TDFN package (1.4x2.0x0.75 mm)
• Industrial -40 ºC to 85 ºC temperature range
Application
• Smart Mobile Handsets
• Multi-mode RF Clock Distribution
• Baseband Peripheral Clock Distribution
Description
The SL18861DI product is a high performance 3 output
clock distribution buffer and provides 3 outputs from a
single input clock by using SLI proprietary low phase
noise and low power dissipation circuit design.
The SL18861DI can be used in baseband mobile RF
applications including WLAN, Bluetooth and DVB-H as an
input clock reference. The product designed to isolate
each device driven by their clock outputs to minimize
interference between these devices.
Each of the clock buffer outputs can be individually
disabled by using OE1/2/3 control pins to reduce the
power consumption if the connected device does not need
the clock. The device operates from single power supply
from 1.70V to 3.65V and from -40 ºC to 85 ºC.
Benefits
• Fast Time-to-market
• Cost Reduction
• Low Power Dissipation
• Low Phase Noise
Block Diagram
CONTROL LOGIC
6
7
5
10
4
8
9
3
2
1
CLKOUT1
CLKOUT2
CLKOUT3
CLKIN
VDD
VSS
OE2
OE3
OE1
OE_OSC
3-Channel Clock Distribution Buffer


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