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TS1001IJ5T Datenblatt(PDF) 11 Page - Silicon Laboratories |
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TS1001IJ5T Datenblatt(HTML) 11 Page - Silicon Laboratories |
11 / 12 page TS1001 Silicon Laboratories, Inc. Page 11 400 West Cesar Chavez, Austin, TX 78701 TS1001 Rev. 1.0 +1 (512) 416-8500 ▪ www.silabs.com PACKAGE OUTLINE DRAWING 5-Pin SC70 Package Outline Drawing (N.B., Drawings are not to scale) Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analog-intensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 1 3 4 5 0.65 TYP. 2 1.30 TYP. 0.15 - 0.30 1.80 - 2.20 1.15 - 1.35 0.26 - 0.46 0.275 - 0.575 2 1 LEAD FRAME THICKNESS GAUGE PLANE 1 2 NOTES: DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. DOES NOT INCLUDE INTER-LEAD FLASH OR PROTRUSIONS. DIE IS FACING UP FOR MOLDING. DIE IS FACING DOWN FOR TRIM/FORM. 3. 5. CONTROLLING DIMENSIONS IN MILIMITERS. ALL SIDE 1.80 - 2.40 0.00 - 0.10 1.00 MAX 0.10 - 0.18 0.15 TYP. 8º - 12º 0º - 8º 0.800 – 0.925 0.40 – 0.55 4 ALL SPECIFICATION COMPLY TO JEDEC SPEC MO-203 AA 6. ALL SPECIFICATIONS REFER TO JEDEC MO-203 AA 7. LEAD SPAN/STAND OFF HEIGHT/COPLANARITY ARE CONSIDERED AS SPECIAL CHARACTERISTIC 0.10 MAX |
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