Si4708/09-C

Rev. 1.2

7

Figure 2. 3-Wire Control Interface Write Timing Parameters

Figure 3. 3-Wire Control Interface Read Timing Parameters

Table 5. 3-Wire Control Interface Characteristics

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

SCLK Frequency

0—

2.5

MHz

SCLK High Time

25

—

—

ns

SCLK Low Time

25

—

—

ns

SDIO Input, SEN to SCLK

Setup

20

—

—

ns

SDIO Input to SCLK

Hold

10

—

—

ns

SEN Input to SCLK

10

—

—

ns

SEN Input to SCLK

Hold

10

—

—

ns

SCLK

to SDIO Output Valid

Read

2

—

25

ns

SCLK

to SDIO Output High Z

Read

2

—

25

ns

Note: When selecting 3-wire Mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the

rising edge of RST.

SCLK

70%

30%

SEN

70%

30%

SDIO

A7

A0

70%

30%

A6-A5,

R/W,

A4-A1

Address In

Data In

D15

D14-D1

D0

½ Cycle Bus

Turnaround

SCLK

70%

30%

SEN

70%

30%

SDIO

80%

20%

Address In

Data Out

A7

A0

A6-A5,

R/W,

A4-A1

D15

D14-D1

D0