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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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ADS8555 Datenblatt(PDF) 5 Page - Texas Instruments |
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ADS8555 Datenblatt(HTML) 5 Page - Texas Instruments |
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5 / 43 page  5 ADS8555 www.ti.com SBAS531D – DECEMBER 2010 – REVISED FEBRUARY 2016 Product Folder Links: ADS8555 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Pin Functions (continued) PIN TYPE(1) DESCRIPTION NAME NO. PARALLEL INTERFACE (PAR/SER = 0) SERIAL INTERFACE (PAR/SER = 1) DB0/SEL_A 17 DIO/DI Word mode (WORD/BYTE = 0): Data bit 0 (LSB) input/output Select SDO_A input. When high, SDO_A is active. When low, SDO_A is disabled. Must always be high. Byte mode (WORD/BYTE = 1): Connect to BGND or BVDD BUSY/INT 18 DO When CR bit C21 = 0 (BUSY/INT), converter busy status output. Transitions high when a conversion starts and remains high during the entire process. Transitions low when the conversion data of all six channels are latched to the output register and remains low thereafter. In sequential mode (SEQ = 1 in the CR), the BUSY output transitions high when a conversion starts and goes low for a single conversion clock cycle (tCCLK) whenever a channel pair conversion completes. When bit C21 = 1 (BUSY/INT in CR), interrupt output. This bit transitions high after a conversion completes and goes low with the first read data access. The polarity of BUSY/INT output can be changed using bit C20 (BUSY L/H) in the control register. CS/FS 19 DI/DI Chip select input. When low, the parallel interface is enabled. When high, the interface is disabled. Frame synchronization. The falling edge of FS controls the frame transfer. RD 20 DI Read data input. When low, the parallel data output is enabled. When high, the data output is disabled. Connect to BGND CONVST_C 21 DI Hardware mode (HW/SW = 0): Conversion start of channel pair C. The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_C[1:0]. Software mode (HW/SW = 1): Conversion start of channel pair C in sequential mode (CR bit C23 = 1) only; connect to BGND or BVDD otherwise CONVST_B 22 DI Hardware mode (HW/SW = 0): Conversion start of channel pair B. The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_B[1:0]. Software mode (HW/SW = 1): Conversion start of channel pair B in sequential mode (CR bit C23 = 1) only; connect to BGND or BVDD otherwise CONVST_A 23 DI Hardware mode (HW/SW = 0): Conversion start of channel pair A. The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_A[1:0]. Software mode (HW/SW = 1): Conversion start of all selected channels except in sequential mode (CR bit C23 = 1): Conversion start of channel pair A only STBY 24 DI Standby mode input. When low, the entire device is powered down (including the internal clock and reference). When high, the device operates in normal mode. AGND 25, 32, 37, 38, 43, 44, 49, 52, 53, 55, 57, 59 P Analog ground, connect to analog ground plane Pin 25 can have a dedicated ground if the difference between its potential and AGND is always kept within ±300 mV. AVDD 26, 34, 35, 40, 41, 46, 47, 50, 60 P Analog power supply (4.5 V to 5.5 V). Decouple each pin with a 100-nF ceramic capacitor to AGND. Use an additional 10- μF capacitor to AGND close to the device but without compromising the placement of the smaller capacitor. Pin 26 can have a dedicated power supply if the difference between its potential and AVDD is always kept within ±300 mV. RANGE/XCLK 27 DI/DIO Hardware mode (HW/SW = 0): Input voltage range select input. When low, the analog input range is ±4 VREF. When high, the analog input range is ±2 VREF. Software mode (HW/SW = 1): External conversion clock input, if CR bit C11 (CLKSEL) is set high or internal conversion clock output, if CR bit C10 (CLKOUT_EN) is set high. If not used, connect to BVDD or BGND. RESET 28 DI Reset input, active high. Aborts any ongoing conversions. Resets the internal control register to 0x000003FF. The RESET pulse must be at least 50 ns long. WORD/BYTE 29 DI Output mode selection input. When low, data are transferred in word mode using DB[15:0]. When high, data are transferred in byte mode using DB[15:8] with the byte order controlled by HBEN pin when two accesses are required for a complete 16-bit transfer. Connect to BGND HVSS 30 P Negative supply voltage for the analog inputs (–16.5 V to –5 V). Decouple with a 10-0nF ceramic capacitor to AGND placed next to the device and a 10- μF capacitor to AGND close to the device but without compromising the placement of the smaller capacitor. HVDD 31 P Positive supply voltage for the analog inputs (5 V to 16.5 V). Decouple with a 100-nF ceramic capacitor to AGND placed next to the device and a 10- μF capacitor to AGND close to the device but without compromising the placement of the smaller capacitor. CH_A0 33 AI Analog input of channel A0. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C26 (RANGE_A) in software mode. CH_A1 36 AI Analog input of channel A1. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C26 (RANGE_A) in software mode. |
Ähnliche Teilenummer - ADS8555_16 |
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Ähnliche Beschreibung - ADS8555_16 |
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