Datenblatt-Suchmaschine für elektronische Bauteile |
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DAC34SH84IZAYR Datenblatt(PDF) 11 Page - Texas Instruments |
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DAC34SH84IZAYR Datenblatt(HTML) 11 Page - Texas Instruments |
11 / 93 page DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 6.8 Timing Requirements – Digital Specifications MIN NOM MAX UNIT CLOCK INPUT (DACCLKP/N) Duty cycle 40% 60% DACCLKP/N input frequency 1500 MHz OUTPUT STROBE (OSTRP/N) fOSTR = fDACCLK / (n x 8 x Interp) where n is any positive fDACCLK / fOSTR Frequency MHz integer, fDACCLK is DACCLK frequency in MHz (8 x interp) Duty cycle 50% DIGITAL INPUT TIMING SPECIFICATIONS Timing LVDS inputs: DAB[15:0]P/N, DCD[15:0]P/N, ISTRP/N, SYNCP/N, PARITYCDP/N, double edge latching Config36 Setting datadly clkdly 0 0 30 0 1 –10 0 2 –50 0 3 –90 Setup time, 0 4 –130 DAB[15:0]P/N, DCD[15:0]P/N, 0 5 –170 ISTRP/N, ISTRP/N and SYNCP/N reset latched ts(DATA) 0 6 –210 SYNCP/N and only on rising edge of DATACLKP/N 0 7 –250 ps PARITYP/N, valid to either edge of 1 0 50 DATACLKP/N 2 0 90 3 0 130 4 0 170 5 0 210 6 0 250 7 0 290 Config36 Setting datadly clkdly 0 0 200 0 1 240 0 2 280 0 3 320 Hold time, 0 4 360 DAB[15:0]P/N, DCD[15:0]P/N, 0 5 400 ISTRP/N, ISTRP/N and SYNCP/N reset latched th(DATA) 0 6 440 ps SYNCP/N and only on rising edge of DATACLKP/N 0 7 480 PARITYP/N, valid after either edge of 1 0 190 DATACLKP/N 2 0 150 3 0 110 4 0 70 5 0 30 6 0 –10 7 0 –50 t(ISTR_SYNC) ISTRP/N and fDATACLK is DATACLK frequency in MHz 1/2fDATACLK ns SYNCP/N pulse width Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: DAC34SH84 |
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