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PEF20570 Datenblatt(PDF) 3 Page - Infineon Technologies AG

Teile-Nr. PEF20570
Beschreibung  DSP Embedded Line and Port Interface Controller
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Hersteller  INFINEON [Infineon Technologies AG]
Homepage  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEF20570 Datenblatt(HTML) 3 Page - Infineon Technologies AG

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PEB 20570/PEF 20570
PEB 20571/PEF 20571
Addendum to “DELIC Clock System Synchronization”
Addendum
3/8
2003-08-04
The time within the DELIC DCXO guarantees the 100 ppm clock accuracy varies,
depending on various conditions. When the central office deactivates, the user will be
notified by the DELIC. It is up to the user to provide another clock source (for example
REFCLK) for the DCXO as soon as possible.
1.2
VIP clocked in LT-T Mode by an external Crystal
Figure 2
Clocking the VIP by using external Crystal
As shown in Figure 2 no unstable system can occur by using an external crystal rather
than the DELIC Layer 1 clock as VIP clock source in LT-T mode. When the central office
line is deactivated, the VIP takes the 15.36 MHz oscillator signal and divides it by 10.
This signal is used as XCLK input of the DELIC DCXO. Since the VIP 15.36 MHz signal
is entirely independent from the DELIC clocking system no unstable system can occur.
Note: In LT-T mode it is recommended to use an external crystal to clock the VIP.
DE LIC _refclk2
VIP
C entra l
Offic e
OS C
Rx P L L
DC X O
/1 0
Mu x
15.36 M H z
16.384 M H z
Divid e r
PD
PL L
D iv ider
1.5 36 M H z
D ivider
8k H z
XC L K
RE FCL K
16.384 M H z
DE LIC
MU X
RE F C L K


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