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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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54F322DM Datenblatt(PDF) 3 Page - National Semiconductor (TI) |
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54F322DM Datenblatt(HTML) 3 Page - National Semiconductor (TI) |
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3 / 10 page  Unit LoadingFan Out 54F74F Pin Names Description UL Input IIH IIL HIGHLOW Output IOH IOL RE Register Enable Input (Active LOW) 1010 20 mA b06 mA SP Serial (HIGH) or Parallel (LOW) Mode Control Input 1010 20 mA b06 mA SE Sign Extend Input (Active LOW) 1030 20 mA b18 mA S Serial Data Select Input 1020 20 mA b12 mA D0 D1 Serial Data Inputs 1010 20 mA b06 mA CP Clock Pulse Input (Active Rising Edge) 1010 20 mA b06 mA MR Asynchronous Master Reset Input (Active LOW) 1010 20 mA b06 mA OE TRI-STATE Output Enable Input (Active LOW) 1010 20 mA b06 mA Q0 Bi-State Serial Output 50333 b 1 mA b20 mA IO0–IO7 Multiplexed Parallel Data Inputs or 351083 70 mA b065 mA TRI-STATE Parallel Data Outputs 15040 (333) b3 mA24 mA (20 mA) Functional Description The ’F322 contains eight D-type edge triggered flip-flops and the interstage gating required to perform right shift and the intrastage gating necessary for hold and synchronous parallel load operations A LOW signal on RE enables shift- ing or parallel loading while a HIGH signal enables the hold mode A HIGH signal on SP enables shift right while a LOW signal disables the TRI-STATE output buffers and en- ables parallel loading In the shift right mode a HIGH signal on SE enables serial entry from either D0 or D1 as deter- mined by the S input A LOW signal on SE enables shift right but Q7 reloads its contents thus performing the sign extend function required for the ’F384 Twos Complement Multiplier A HIGH signal on OE disables the TRI-STATE output buff- ers regardless of the other control inputs In this condition the shifting and loading operations can still be performed Mode Select Table Mode Inputs Outputs Q0 MR RE SP SE SOE CP IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 Clear L X X X X L X L L L L L L L L L L X X X X H X Z ZZZZZZZ L Parallel HL L X X X L I7 I6 I5 I4 I3 I2 I1 I0 I0 Load Shift H L H H L L L D0 O7 O6 O5 O4 O3 O2 O1 O1 Right H L H H H L L D1 O7 O6 O5 O4 O3 O2 O1 O1 Sign HL H L X L L O7 O7 O6 O5 O4 O3 O2 O1 O1 Extend Hold H H X X X L L NC NC NC NC NC NC NC NC NC When the OE input is HIGH all IOn terminals are at the high impedance state sequential operation or clearing of the register is not affected Note 1 I7–I0 e The level of the steady-state input at the respective IO terminal is loaded into the flip-flop while the flip-flop outputs (except Q0) are isolated from the IO terminal Note 2 D0 D1 e The level of the steady-state inputs to the serial multiplexer input Note 3 O7–O0 e The level of the respective Qn flip-flop prior to the last Clock LOW-to-HIGH transition H e HIGH Voltage Level L e LOW Voltage Level Z e High Impedance Output State L e LOW-to-HIGH Transition NC e No Change 3 |
Ähnliche Teilenummer - 54F322DM |
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Ähnliche Beschreibung - 54F322DM |
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