Datenblatt-Suchmaschine für elektronische Bauteile |
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TDA5103A Datenblatt(PDF) 10 Page - Infineon Technologies AG |
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TDA5103A Datenblatt(HTML) 10 Page - Infineon Technologies AG |
10 / 29 page Functional Description 3 - 3 TDA 5103A preliminary Wireless Components Specification, March 2001 3.2 Pin Definitions and Functions Table 3-2 Pin No. Symbol Interface Schematic Function 1 PDWN Disable pin for the complete transmitter cir- cuit. A logic low (PDWN < 0.7 V) turns off all transmitter functions. A logic high (PDWN > 1.5 V) gives access to all transmitter functions. PDWN input will be pulled up by 40 µA inter- nally by setting DATA to a logic high-state. 2 VS This pin is the positive supply of the trans- mitter electronics. An RF bypass capacitor should be con- nected directly to this pin and returned to GND (pin 3) as short as possible. 3 GND General ground connection. 4 LF Output of the charge pump and input of the VCO control voltage. The loop bandwidth of the PLL is 150 kHz when only the internal loop filter is used. The loop bandwidth may be reduced by applying an external RC network referencing to the positive supply VS (pin 2). 1 V S 150 k Ω 5 k Ω 250 k Ω "O N " 40 µA ∗ DATA V S 10 k Ω 4 35 k Ω 15 pF 140 pF |
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