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UT06MRA075 Datenblatt(PDF) 8 Page - Aeroflex Circuit Technology |
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UT06MRA075 Datenblatt(HTML) 8 Page - Aeroflex Circuit Technology |
8 / 16 page 8 PHYSICAL DESIGN Using three layers of metal interconnect, Aeroflex achieves optimized layouts that maximize speed of critical nets, overall chip performance, and design density up to 500,000 equivalent gates. Test Capability Aeroflex supports all phases of test development from test stim- ulus generation through high-speed production test. This support includes ATPG, fault simulation, and fault grading. Scan design options are available on all UT0.6 CRH storage ele- ments. Automatic test program development capabilities handle large vector sets for use with Aeroflex’s Teradyne Tiger tester supporting high-speed testing (up to 1.2GHz with pin multiplexing). Unparalleled Quality and Reliability Aeroflex is dedicated to meeting the stringent performance re- quirements of aerospace and defense systems suppliers. Aeroflex maintains the highest level of quality and reliability through our Quality Management Program under MIL-PRF- 38535 and ISO-9001. In 1988, we were the first gate array man- ufacturer to achieve QPL certification and qualification of our technology families. Our product assurance program has kept pace with the demands of certification and qualification. Our quality management plan includes the following activities and initiatives. Quality improvement plan Failure analysis program SPC plan Corrective action plan Change control program Standard Evaluation Circuit (SEC) and Technology Charac- terization Vehicle (TCV) assessment program Certification and qualification program Because of numerous product variations permitted with custom- er specific designs, much of the reliability testing is performed using a Standard Evaluation Circuit (SEC) and Technology Characterization Vehicle (TCV). The TCV utilizes test struc- tures to evaluate hot carrier aging, electromigration, and time dependent test samples for reliability testing. Data from the wa- fer-level testing can provide rapid feedback to the fabrication process, as well as establish the reliability performance of the product before it is packaged and shipped. Radiation Tolerance Aeroflex incorporates radiation-tolerance techniques in process design, design rules, array design, power distribution, and li- brary element design. All key radiation-tolerance process parameters are controlled and monitored using statistical meth- ods and in-line testing. Notes: 1. Total dose Co-60 testing is in accordance with MIL-STD-883, Method 1019. Data sheet electrical characteristics guaranteed to 1.0E5 rads(Si O2). All post-radiation values measured at 25C. 2. Total dose Co-60 testing is in accordance with MIL-STD-883, Method 1019 at dose rates <1 rad(Si O2)/s. 3. Short pulse 20ns FWHM (full width, half maximum). 4. Is design dependent; SEU limit based on standard evaluation circuit at 4.5V worst case condition. 5. SEU-hard flip-flop cell. Non-hard flip-flop typical is 4E-8. PARAMETER RADIATION TOLERANCE NOTES Total dose 1.0E5 rad(SiO2) 3.0E5 rad(SiO2) 1 2 Dose rate upset 1.0E8 rad(Si)/sec 3 Dose rate survivability 1.0E11 rad(Si)/sec 4 SEU <2.0E-10 errors per cell-day 4, 5 Projected neutron fluence 1.0E14 n/sq cm Latchup Latchup-immune over speci- fied use conditions |
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Ähnliche Beschreibung - UT06MRA075 |
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