Datenblatt-Suchmaschine für elektronische Bauteile |
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ADC10030CIVT Datenblatt(PDF) 10 Page - National Semiconductor (TI) |
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ADC10030CIVT Datenblatt(HTML) 10 Page - National Semiconductor (TI) |
10 / 17 page Specification Definitions (Continued) positive full scale (11⁄2 LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value. OUTPUT DELAY is the time delay after the fall of the input clock before the data update is present at the output pins. OUTPUT HOLD TIME is the length of time that the output data is valid after the fall of the input clock. PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that data is pre- sented to the output driver stage. Data for any given sample is available by the Pipeline Delay plus the Output Delay after that sample is taken. New data is available at every clock cycle, but the data lags the conversion by the Pipeline Delay plus the Output Delay. PSRR (POWER SUPPLY REJECTION RATIO) is the ratio of the change in dc power supply voltage to the resulting change in Full Scale Error, expressed in dB. SAMPLING (APERTURE) DELAY or APERTURE TIME is that time required after the fall of the clock input for the sam- pling switch to open. The sample is effectively taken this amount of time after the fall of the clock input. SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the RMS value of the input signal to the RMS value of other spectral components below half the clock frequency, not including harmonics or dc. SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio, expressed in dB, of the RMS value of the input signal to the RMS value of all of the other spectral com- ponents below half the clock frequency, including harmonics but excluding dc. SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ- ence, expressed in dB or dBc, between the RMS value of the input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum that is not present at the input. TOTAL HARMONIC DISTORTION (THD) is the ratio, ex- pressed in dB, of the RMS total of the first six harmonic com- ponents, to the RMS value of the input signal. ZERO SCALE OFFSET ERROR is the difference between the ideal input voltage (1⁄2 LSB) and the actual input voltage that just causes a transition from an output code of zero to an output code of one. Timing Diagram DS101064-15 FIGURE 1. ADC10030 Timing Diagram www.national.com 10 |
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Ähnliche Beschreibung - ADC10030CIVT |
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