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ADC10662CIWM Datenblatt(PDF) 11 Page - National Semiconductor (TI) |
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ADC10662CIWM Datenblatt(HTML) 11 Page - National Semiconductor (TI) |
11 / 14 page Applications Information (Continued) 4.0 INHERENT SAMPLE-AND-HOLD Because the ADC10662 and ADC10664 sample the input signal once during each conversion, they are capable of measuring relatively fast input signals without the help of an external sample-hold. In a non-sampling successive-approximation A/D converter, regardless of speed, the input signal must be stable to better than ±1/2 LSB during each conversion cycle or significant errors will result. Consequently, even for many relatively slow input sig- nals, the signals must be externally sampled and held con- stant during each conversion if a SAR with no internal sample-and-hold is used. Because they incorporate a direct sample/hold control input, the ADC10662 and ADC10664 are suitable for use in DSP-based systems. The S /H input allows synchronization of the A/D converter to the DSP system’s sampling rate and to other ADC10662s, and ADC10664s. The ADC10662 and ADC10664 can perform accurate con- versions of input signals with frequency components from DC to over 250 kHz. 5.0 POWER SUPPLY CONSIDERATIONS The ADC10662 and ADC10664 are designed to operate from a +5V (nominal) power supply. There are two supply pins, AV CC and DVCC. These pins allow separate external bypass capacitors for the analog and digital portions of the circuit. To guarantee accurate conversions, the two supply pins should be connected to the same voltage source, and each should be bypassed with a 0.1 µF ceramic capacitor in parallel with a 10 µF tantalum capacitor. Depending on the circuit board layout and other system considerations, more bypassing may be necessary. The ADC10662 and ADC10664 have separate analog and digital ground pins for separate bypassing of the analog and digital supplies. Their ground pins should be connected to the same potential, and all grounds should be “clean” and free of noise. In systems with multiple power supplies, careful attention to power supply sequencing may be necessary to avoid over- driving inputs. The A/D converter’s power supply pins should be at the proper voltage before digital or analog signals are applied to any of the other pins. 6.0 LAYOUT AND GROUNDING In order to ensure fast, accurate conversions from the ADC10662 and ADC10664, it is necessary to use appropri- ate circuit board layout techniques. The analog ground re- turn path should be low-impedance and free of noise from other parts of the system. Noise from digital circuitry can be especially troublesome, so digital grounds should always be separate from analog grounds. For best performance, sepa- rate ground planes should be provided for the digital and analog parts of the system. All bypass capacitors should be located as close to the con- verter as possible and should connect to the converter and to ground with short traces. The analog input should be iso- lated from noisy signal traces to avoid having spurious sig- nals couple to the input. Any external component (e.g., a fil- ter capacitor) connected across the converter’s input should be connected to a very clean ground return point. Grounding the component at the wrong point will result in reduced con- version accuracy. 7.0 DYNAMIC PERFORMANCE Many applications require the A/D converter to digitize AC signals, but conventional DC integral and differential nonlin- earity specifications don’t accurately predict the A/D convert- er’s performance with AC input signals. The important speci- fications for AC applications reflect the converter’s ability to digitize AC signals without significant spectral errors and without adding noise to the digitized signal. Dynamic charac- teristics such as signal-to-noise ratio (SNR) and total har- monic distortion (THD), are quantitative measures of this ca- pability. DS011192-13 FIGURE 4. Typical Connection. Note the multiple bypass capacitors on the reference and power supply pins. If V REF− is not grounded, it should also be bypassed to analog ground using multiple capacitors (see 5.0 “Power Supply Considerations”). AGND and DGND should be at the same potential. V IN0 is shown with an input protection network. www.national.com 11 |
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