DAC7551-Q1

SLAS767B – JUNE 2011 – REVISED MARCH 2015

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6.2 ESD Ratings

VALUE

UNIT

±2000

All pins

±500

Electrostatic discharge

V

Charged-device model (CDM), per AEC

Corner pins (1, 6, 7, and

Q100-011

±750

12)

(1)

AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

2.7

5.5

0.25

0

GND

0

Input voltage

1.8

V

CLR

0

SYNC

0

SCLK

0

SDIN

0

SDO

0

Output voltage

V

0

Operating junction temperature

150

°C

6.4 Thermal Information

DRN (USON)

UNIT

12 PINS

Junction-to-ambient thermal resistance

49.8

Junction-to-case (top) thermal resistance

45.8

Junction-to-board thermal resistance

18.2

°C/W

Junction-to-top characterization parameter

0.8

Junction-to-board characterization parameter

18.3

Junction-to-case (bottom) thermal resistance

2.9

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

GND (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Resolution

12

Bits

Relative accuracy

±0.35

±1

LSB

Differential nonlinearity

Specified monotonic by design

±0.08

±0.5

LSB

Offset error

±12

mV

Zero-scale error

All zeroes loaded to DAC register

±12

mV

Gain error

±0.15

%FSR

Full-scale error

±0.5

%FSR

Zero-scale error drift

7

μV/°C

ppm of

Gain temperature coefficient

3

FSR/°C

(1)

Linearity tested using a reduced code range of 30 to 4065; output unloaded.

4

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