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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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FM24V01A-G Datenblatt(PDF) 5 Page - Cypress Semiconductor |
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FM24V01A-G Datenblatt(HTML) 5 Page - Cypress Semiconductor |
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5 / 19 page  FM24V01A Document Number: 001-90869 Rev. *H Page 5 of 19 If during operation the power supply drops below the specified VDD minimum, the system should issue a START condition prior to performing another operation. Data/Address Transfer All data transfers (including addresses) take place while the SCL signal is HIGH. Except under the three conditions described above, the SDA signal should not change while SCL is HIGH. Acknowledge / No-acknowledge The acknowledge takes place after the 8th data bit has been transferred in any transaction. During this state, the transmitter should release the SDA bus to allow the receiver to drive it. The receiver drives the SDA signal LOW to acknowledge receipt of the byte. If the receiver does not drive SDA LOW, the condition is a no-acknowledge and the operation is aborted. The receiver will fail to acknowledge for two distinct reasons, the first being that a byte transfer fails. In this case, the no-acknowledge ceases the current operation so that the part can be addressed again. This allows the last byte to be recovered in the event of a communication error. The second and most common reason is that, the receiver does not acknowledge to deliberately end an operation. For example, during a read operation, the FM24V01A will continue to place data on the bus as long as the receiver sends acknowledges (and clocks). When a read operation is complete and no more data is needed, the receiver must not acknowledge the last byte. If the receiver acknowledges the last byte, this causes the FM24V01A to attempt to drive the bus on the next clock while the master is sending a new command such as STOP. Figure 3. START and STOP Conditions full pagewidth SDA SCL P STOP Condition SDA SCL S START Condition Figure 4. Data Transfer on the I2C Bus handbook, full pagewidth S or P SDA S P SCL STOP or START condition S START condition 2 3 4 - 8 9 ACK 9 ACK 78 12 MSB Acknowledgement signal from slave Byte complete Acknowledgement signal from receiver 1 Figure 5. Acknowledge on the I2C Bus handbook, full pagewidth S START Condition 9 8 2 1 Clock pulse for acknowledgement No Acknowledge Acknowledge DATA OUTPUT BY MASTER DATA OUTPUT BY SLAVE SCL FROM MASTER |
Ähnliche Teilenummer - FM24V01A-G |
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Ähnliche Beschreibung - FM24V01A-G |
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