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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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FM24V02A-G Datenblatt(PDF) 8 Page - Cypress Semiconductor |
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FM24V02A-G Datenblatt(HTML) 8 Page - Cypress Semiconductor |
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8 / 19 page  FM24V02A Document Number: 001-90839 Rev. *G Page 8 of 19 Read Operation There are two basic types of read operations. They are current address read and selective address read. In a current address read, the FM24V02A uses the internal address latch to supply the address. In a selective read, the user performs a procedure to set the address to a specific value. Current Address & Sequential Read As mentioned above the FM24V02A uses an internal latch to supply the address for a read operation. A current address read uses the existing value in the address latch as a starting place for the read operation. The system reads from the address immediately following that of the last operation. To perform a current address read, the bus master supplies a slave address with the LSB set to a '1'. This indicates that a read operation is requested. After receiving the complete slave address, the FM24V02A will begin shifting out data from the current address on the next clock. The current address is the value held in the internal address latch. Beginning with the current address, the bus master can read any number of bytes. Thus, a sequential read is simply a current address read with multiple byte transfers. After each byte the internal address counter will be incremented. Note Each time the bus master acknowledges a byte, this indicates that the FM24V02A should read out the next sequential byte. There are four ways to properly terminate a read operation. Failing to properly terminate the read will most likely create a bus contention as the FM24V02A attempts to read out additional data onto the bus. The four valid methods are: 1. The bus master issues a no-acknowledge in the 9th clock cycle and a STOP in the 10th clock cycle. This is illustrated in the diagrams below. This is preferred. 2. The bus master issues a no-acknowledge in the 9th clock cycle and a START in the 10th. 3. The bus master issues a STOP in the 9th clock cycle. 4. The bus master issues a START in the 9th clock cycle. If the internal address reaches 7FFFh, it will wrap around to 0000h on the next read cycle. Figure 11 and Figure 12 show the proper operation for current address reads. Figure 10. Hs-Mode Byte Write S A Slave Address 0 Data Byte A P By Master By F-RAM Start & Enter Hs-mode Address & Data Stop & Exit Hs-mode S 1 Start Acknowledge X X X 1 0 0 0 0 Hs-mode command Address MSB A Address LSB A No Acknowledge Figure 11. Current Address Read Figure 12. Sequential Read S A Slave Address 1 Data Byte 1 P By Master By F-RAM Start Address Stop Acknowledge No Acknowledge Data S A Slave Address 1 Data Byte 1 P By Master By F-RAM Start Address Stop Acknowledge No Acknowledge Data Data Byte A Acknowledge |
Ähnliche Teilenummer - FM24V02A-G |
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Ähnliche Beschreibung - FM24V02A-G |
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