FM25V01A

Document Number: 001-90881 Rev. *E

Page 3 of 22

Pinout

Figure 1. 8-pin SOIC Pinout

Pin Definitions

Pin Name

I/O Type

Description

SCK

Input

Serial Clock. All I/O activity is synchronized to the serial clock. Inputs are latched on the rising edge

and outputs occur on the falling edge. Because the device is synchronous, the clock frequency may

be any value between 0 and 40 MHz and may be interrupted at any time.

CS

Input

Chip Select. This active LOW input activates the device. When HIGH, the device enters low-power

standby mode, ignores other inputs, and the output is tristated. When LOW, the device internally

activates the SCK signal. A falling edge on CS must occur before every opcode.

SI[1]

Input

Serial Input. All data is input to the device on this pin. The pin is sampled on the rising edge of SCK

tions.

SO[1]

Output

Serial Output. This is the data output pin. It is driven during a read and remains tristated at all other

times including when HOLD is LOW. Data transitions are driven on the falling edge of the serial clock.

WP

Input

Write Protect. This active LOW pin prevents write operation to the Status Register when WPEN is

set to ‘1’. This is critical because other write protection features are controlled through the Status

Register. A complete explanation of write protection is provided on Status Register and Write

HOLD

Input

HOLD Pin. The HOLD pin is used when the host CPU must interrupt a memory operation for another

task. When HOLD is LOW, the current operation is suspended. The device ignores any transition

on SCK or CS. All transitions on HOLD must occur while SCK is LOW. This pin has a weak internal

Power supply Ground for the device. Must be connected to the ground of the system.

Power supply Power supply input to the device.

HOLD

SCK

1

2

3

4

5

CS

8

7

6

VDD

SI

SO

Top View

not to scale

VSS

WP

Note

1. SI may be connected to SO for a single pin data interface

.