Datenblatt-Suchmaschine für elektronische Bauteile |
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KMPC870ZT66 Datenblatt(PDF) 2 Page - Freescale Semiconductor, Inc |
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KMPC870ZT66 Datenblatt(HTML) 2 Page - Freescale Semiconductor, Inc |
2 / 84 page MPC875/MPC870 Hardware Specifications, Rev. 3.0 2 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Features Table 1 shows the functionality supported by the members of the MPC875/MPC870. 2Features The MPC875/870 is comprised of three modules that each use the 32-bit internal bus: a MPC8xx core, a system integration unit (SIU), and a communications processor module (CPM). The following list summarizes the key MPC875/870 features: • Embedded MPC8xx core up to 133 MHz • Maximum frequency operation of the external bus is 80 MHz (in 1:1 mode) — The 133-MHz core frequency supports 2:1 mode only. — The 66-/80-MHz core frequencies support both the 1:1 and 2:1 modes. • Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with thirty-two 32-bit general-purpose registers (GPRs) — The core performs branch prediction with conditional prefetch and without conditional execution. — 8-Kbyte data cache and 8-Kbyte instruction cache (see Table 1) – Instruction cache is two-way, set-associative with 256 sets in 2 blocks – Data cache is two-way, set-associative with 256 sets – Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache blocks. – Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and are lockable on a cache block basis. — MMUs with 32-entry TLB, fully associative instruction and data TLBs — MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address spaces and 16 protection groups — Advanced on-chip emulation debug mode • Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits) • 32 address lines • Memory controller (eight banks) — Contains complete dynamic RAM (DRAM) controller — Each bank can be a chip select or RAS to support a DRAM bank. — Up to 30 wait states programmable per memory bank — Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory devices — DRAM controller programmable to support most size and speed memory interfaces — Four CAS lines, four WE lines, and one OE line Table 1. MPC875/870 Devices Part Cache Ethernet SCC SMC USB Security Engine I Cache D Cache 10BaseT 10/100 MPC875 8 Kbyte 8 Kbyte 1 2 1 1 1 Yes MPC870 8 Kbyte 8 Kbyte — 2 — 1 1 No |
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