ADC10080

SNAS177H – JULY 2003 – REVISED MARCH 2013

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Table 1. PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS (continued)

Pin No.

Symbol

Equivalent Circuit

Description

DIGITAL I/O

Digital clock input. The range of frequencies for this input is 20 MHz

1

CLK

to 80 MHz. The input is sampled on the rising edge of this input.

DF = “1” Two’s Complement

15

DF

DF = “0” Offset Binary

This is the standby pin. When high, this pin sets the converter into

28

STBY

standby mode. When this pin is low, the converter is in active mode.

IRS (Input Range

5

Select)

16–20,

Digital output data. D0 is the LSB and D9 is the MSB of the binary

D0–D9

23–27

output word.

ANALOG POWER

Positive analog supply pins. These pins should be connected to a

quiet 3.0V source and bypassed to analog ground with a 0.1 µF

2, 9, 10

monolithic capacitor located within 1 cm of these pins. A 4.7 µF

capacitor should also be used in parallel.

3, 11, 14

Ground return for the analog supply.

DIGITAL POWER

Positive digital supply pins for the ADC10080's output drivers. This

pin should be bypassed to digital ground with a 0.1 µF monolithic

22

capacitor located within 1 cm of this pin. A 4.7 µF capacitor should

also be used in parallel. The voltage on this pin should never exceed

The ground return for the digital supply for the output drivers. This

21

pin should be connected to the ground plane, but not near the

analog circuitry.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

4

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