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ADC08L060 Datenblatt(PDF) 6 Page - Texas Instruments

Teilenummer ADC08L060
Bauteilbeschribung  10 MSPS to 60 MSPS, 0.65 mW/MSPS A/D Converter with Internal Sample-and-Hold
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ADC08L060
SNAS167G – MAY 2002 – REVISED MARCH 2013
www.ti.com
Converter Electrical Characteristics (continued)
The following specifications apply for VA = VDR = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 10 pF, fCLK = 60 MHz at 50% duty
cycle. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C
(1)(2) (3)
Typical
Limits
Units
Symbol
Parameter
Conditions
(4)
(4)
(Limits)
CLK, PD DIGITAL INPUT CHARACTERISTICS
VIH
Logical High Input Voltage
VDR = VA = 3.6V
2.0
V (min)
VIL
Logical Low Input Voltage
VDR = VA = 2.7V
0.8
V (max)
IIH
Logical High Input Current
VIH = VDR = VA = 3.6V
10
nA
IIL
Logical Low Input Current
VIL = 0V, VDR = VA = 2.7V
−50
nA
CIN
Logic Input Capacitance
3
pF
DIGITAL OUTPUT CHARACTERISTICS
VOH
High Level Output Voltage
VA = VDR = 2.7V, IOH = −400 µA
2.6
2.4
V (min)
VOL
Low Level Output Voltage
VA = VDR = 2.7V, IOL = 1.0 mA
0.4
0.5
V (max)
DYNAMIC PERFORMANCE
fIN = 10.1 MHz, VIN = FS − 0.25 dB
7.6
6.9
Bits (min)
ENOB
Effective Number of Bits
fIN = 29 MHz, VIN = FS − 0.25 dB
7.4
Bits
fIN = 10.1 MHz, VIN = FS − 0.25 dB
47.4
43.3
dB (min)
SINAD
Signal-to-Noise & Distortion
fIN = 29 MHz, VIN = FS − 0.25 dB
46.1
dB
fIN = 10.1 MHz, VIN = FS − 0.25 dB
48
44.5
dB (min)
SNR
Signal-to-Noise Ratio
fIN = 29 MHz, VIN = FS − 0.25 dB
47.2
dB
fIN = 10.1 MHz, VIN = FS − 0.25 dB
59.1
dBc
SFDR
Spurious Free Dynamic Range
fIN = 29 MHz, VIN = FS − 0.25 dB
54.5
dBc
fIN = 10.1 MHz, VIN = FS − 0.25 dB
−56.9
dBc
THD
Total Harmonic Distortion
fIN = 29 MHz, VIN = FS − 0.25 dB
−53.3
dBc
fIN = 10.1 MHz, VIN = FS − 0.25 dB
-61.1
dBc
HD2
2nd Harmonic Distortion
fIN = 29 MHz, VIN = FS − 0.25 dB
−54.9
dBc
fIN = 10.1 MHz, VIN = FS − 0.25 dB
−64.2
dBc
HD3
3rd Harmonic Distortion
fIN = 29 MHz, VIN = FS − 0.25 dB
−63.1
dBc
f1 = 11 MHz, VIN = FS − 6.25 dB
IMD
Intermodulation Distortion
−55
dBc
f2 = 12 MHz, VIN = FS − 6.25 dB
POWER SUPPLY CHARACTERISTICS
DC Input
13
15.9
mA (max)
IA
Analog Supply Current
fIN = 10 MHz, VIN = FS − 3 dB
14
mA
DC Input
0.04
0.2
mA (max)
DRID
Output Driver Supply Current
fIN = 10 MHz, VIN = FS − 3 dB
(5)
4.2
mA
DC Input
13
16.1
mA (max)
fIN = 10 MHz, VIN = FS − 3 dB, PD =
IA + DRID
Total Operating Current
18.2
mA
Low
CLK Low, PD = Hi
0.33
mA
DC Input
39
48.3
mW (max)
fIN = 10 MHz, VIN = FS − 3 dB, PD =
mW
PC
Power Consumption
53
Low
CLK Low, PD = Hi
1
mW
FSE change with 2.7V to 3.3V change in
PSRR1
Power Supply Rejection Ratio
−51
dB
VA
SNR reduction with 200 mV at 1MHz on
PSRR2
Power Supply Rejection Ratio
45
dB
supply
(5)
IDR is the current consumed by the switching of the output drivers and is primarily determined by the load capacitance on the output
pins, the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent), IDR = VDR (CO x fO + C1 x f1
+ … + C71 x f7) where VDR is the output driver power supply voltage, Cn is the total capacitance on any given output pin, and fn is the
average frequency at which that pin is toggling.
6
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