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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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ADS8471IRGZTG4 Datenblatt(PDF) 7 Page - Texas Instruments |
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ADS8471IRGZTG4 Datenblatt(HTML) 7 Page - Texas Instruments |
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7 / 31 page  www.ti.com TIMING CHARACTERISTICS ADS8471 SLAS517 – DECEMBER 2007 All specifications typical at –40 °C to 85°C, +VA = 5 V +VBD = 3 V (1) (2) (3) PARAMETER MIN TYP MAX UNIT t(CONV) Conversion time 67 700 ns t(ACQ) Acquisition time 270 300 ns t(HOLD) Sample capacitor hold time 25 ns tpd1 CONVST low to BUSY high 40 ns tpd2 Propagation delay time, end of conversion to BUSY low 25 ns tpd3 Propagation delay time, start of convert state to rising edge of BUSY 25 ns tw1 Pulse duration, CONVST low 40 ns tsu1 Setup time, CS low to CONVST low 20 ns tw2 Pulse duration, CONVST high 20 ns CONVST falling edge jitter 10 ps tw3 Pulse duration, BUSY signal low t(ACQ)min ns tw4 Pulse duration, BUSY signal high 700 ns th1 Hold time, first data bus transition (RD low, or CS low for read cycle, or BYTE input 40 ns changes) after CONVST low td1 Delay time, CS low to RD low 0 ns tsu2 Setup time, RD high to CS high 0 ns tw5 Pulse duration, RD low 50 ns ten Enable time, RD low (or CS low for read cycle) to data valid 30 ns td2 Delay time, data hold from RD high 5 ns td3 Delay time, BYTE rising edge or falling edge to data valid 10 30 ns tw6 Pulse duration, RD high 20 ns tw7 Pulse duration, CS high 20 ns th2 Hold time, last RD (or CS for read cycle ) rising edge to CONVST falling edge 50 ns tpd4 Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling 0 ns edge td4 Delay time, BYTE edge to edge skew 0 ns tsu3 Setup time, BYTE or transition to RD falling edge 10 ns th3 Hold time, BYTE or transition to RD falling edge 10 ns tdis Disable time, RD high (CS high for read cycle) to 3-stated data bus 30 ns td5 Delay time, BUSY low to MSB data valid delay 0 ns td6 Delay time, CS rising edge to BUSY falling edge 50 ns td7 Delay time, BUSY falling edge to CS rising edge 50 ns tsu5 BYTE transition setup time, from BYTE transition to next BYTE transition 50 ns tsu(ABORT) Setup time from the falling edge of CONVST (used to start the valid conversion) to the next falling edge of CONVST (when CS = 0 and CONVST are used to abort) or to the 60 600 ns next falling edge of CS (when CS is used to abort). (1) All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2. (2) See timing diagrams. (3) All timing are measured with 20-pF equivalent loads on all data bits and BUSY pins. Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): ADS8471 |
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Ähnliche Beschreibung - ADS8471IRGZTG4 |
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