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DAC1208LCJ-1 Datenblatt(PDF) 6 Page - Texas Instruments

Teilenummer DAC1208LCJ-1
Bauteilbeschribung  DAC1231/DAC1232 12-Bit, mP Compatible,Double-Buffered D to A Converters
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Hersteller  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DAC1208LCJ-1 Datenblatt(HTML) 6 Page - Texas Instruments

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Definition of Package Pinouts
CONTROL SIGNALS
(all control signals are level actuated)
CS
Chip Select (active low) The CS will enable WR1
WR1
Write 1 The active low WR1 is used to load the digital
data bits (DI) into the input latch The data in the input latch
is latched when WR1 is high The 12-bit input latch is split
into two latches One holds the first 8 bits while the other
holds 4 bits The Byte 1Byte 2 control pin is used to select
both latches when Byte 1Byte 2 is high or to overwrite the
4-bit input latch when in the low state
Byte 1Byte 2
Byte Sequence Control When this control is
high all 12 locations of the input latch are enabled When
low only the four least significant locations of the input latch
are enabled
WR2
Write 2 (active low) The WR2 will enable XFER
XFER
Transfer Control Signal (active low) This signal in
combination with WR2 causes the 12-bit data which is
available in the input latches to transfer to the DAC register
DI0 to DI11 Digital Inputs DI0 is the least significant digital
input (LSB) and DI11 is the most significant digital input
(MSB)
IOUT1 DAC Current Output 1 IOUT1 is a maximum for a
digital code of all 1s in the DAC register and is zero for all
0s in the DAC register
IOUT2 DAC Current Output 2 IOUT2 is a constant minus
IOUT1 orIOUT1aIOUT2econstant (for a fixed reference
voltage) This constant current is
VREF c
1b 14096J
divided by the reference input resistance
RFb Feedback Resistor The feedback resistor is provided
on the IC chip for use as the shunt feedback resistor for the
external op amp which is used to provide an output voltage
for the DAC This on-chip resistor should always be used
(not an external resistor) since it matches the resistors in
the on-chip R-2R ladder and tracks these resistors over
temperature
VREF Reference Voltage Input This input connects an ex-
ternal precision voltage source to the internal R-2R ladder
VREF can be selected over the range of 10V to b10V This
is also the analog voltage input for a 4-quadrant multiplying
DAC application
VCC Digital Supply Voltage This is the power supply pin for
the part VCC can be from 5 VDC to 15 VDC Operation is
optimum for 15 VDC
GND
Pins 3 and 12 of the DAC1208 DAC1209 and
DAC1210 must be connected to ground Pins 3 and 10 of
the DAC1230 DAC1231 and DAC1232 must be connected
to ground It is important that IOUT1 and IOUT2 are at ground
potential for current switching applications Any difference
of potential (VOS on these pins) will result in a linearity
change of
VOS
3VREF
For example if VREF e 10V and these ground pins are 9
mV offset from IOUT1 and IOUT2 the linearity change will be
003%
Definition of Terms
Resolution
Resolution is defined as the reciprocal of the
number of discrete steps in the DAC output It is directly
related to the number of switches or bits within the DAC For
example the DAC1208 has 212 or 4096 steps and therefore
has 12-bit resolution
Linearity Error
Linearity error is the maximum deviation
from a
straight line passing through the endpoints of the
DAC transfer characteristic It is measured after adjusting
for zero and full-scale Linearity error is a parameter intrinsic
to the device and cannot be externally adjusted
National’s linearity test (a) and the best straight line test (b)
used by other suppliers are illustrated below The best
straight line (b) requires a special zero and FS adjustment
for each part which is almost impossible for the user to
determine The end point test uses a standard zero FS ad-
justment procedure and is a much more stringent test for
DAC linearity
Power Supply Sensitivity
Power supply sensitivity is a
measure of the effect of power supply changes on the DAC
full-scale output
Settling Time
Full-scale current settling time requires zero
to full-scale or full-scale to zero output change Settling time
is the time required from a code transition until the DAC
output reaches within g
LSB of the final output value
Full-Scale Error
Full-scale error is a measure of the output
error between an ideal DAC and the actual device output
Ideally for the DAC1208 or DAC1230 series full-scale is
VREFb1 LSB For VREFe10V and unipolar operation
VFULL-SCALEe100000Vb244 mVe99976V
Full-scale
error is adjustable to zero
Differential Non-Linearity
The difference between any
two consecutive codes in the transfer curve from the theo-
retical 1 LSB is differential non-linearity
Monotonic
If the output of a DAC increases for increasing
digital input code then the DAC is monotonic A 12-bit DAC
which is monotonic to 12 bits simply means that input in-
creasing digital input codes will produce an increasing ana-
log output
TLH5690 – 5
a) End Point Test After Zero
and FS Adjust
b) Shifting FS Adjust to Pass
Best Straight Line Test
5


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