CD54HC30F datasheet(5/18 Pages) TI1

Teilenummer	CD54HC30F

Bauteilbeschribung	High Speed CMOS Logic 8-Input NAND Gate

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5

Transition Times (Figure 1)

tTLH, tTHL CL = 50pF

2

-

75

-

95

-

110

ns

4.5

-

15

-

19

-

22

ns

6

-

13

-

16

-

19

ns

Input Capacitance

CI

-

10

-

10

-

10

pF

Power Dissipation Capacitance

(Notes 3, 4)

CPD

-

5

-

25

-

----

pF

HCT TYPES

Propagation Delay, Input to

Output (Figure 2)

tRHL, tPHL CL = 50pF

4.5

-

28

-

35

-

42

ns

Propagation Delay, Data Input to

Output Y

tPLH, tPHL CL = 15pF

5

-

11

-

----

ns

Transition Times (Figure 2)

tTLH, tTHL CL = 50pF

4.5

-

15

-

19

-

22

ns

Input Capacitance

CI

-

10

-

10

-

10

pF

Power Dissipation Capacitance

(Notes 3, 4)

CPD

-

5

-

26

-

----

pF

NOTES:

3. CPD is used to determine the dynamic power consumption, per gate.

4. PD = VCC

2 f

i (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

Switching Speciﬁcations Input tr, tf = 6ns (Continued)

PARAMETER

SYMBOL

TEST

CONDITIONS

VCC

(V)

25oC

-40oC TO 85oC

-55oC TO 125oC

UNITS

MIN

TYP

MAX

MIN

MAX

MIN

MAX

Test Circuits and Waveforms

FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

tPHL

tPLH

tTHL

tTLH

90%

50%

10%

50%

10%

INVERTING

OUTPUT

INPUT

GND

VCC

tr = 6ns

tf = 6ns

90%

tPHL

tPLH

tTHL

tTLH

2.7V

1.3V

0.3V

1.3V

10%

INVERTING

OUTPUT

INPUT

GND

3V

tr = 6ns

tf = 6ns

90%

CD54/74HC30, CD54/74HCT30

Ähnliche Beschreibung - CD54HC30F

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