CDC509

3.3V PHASELOCK LOOP CLOCK DRIVER

SCAS576C − JULY 1996 − REVISED DECEMBER 2004

3

POST OFFICE BOX 655303

Terminal Functions

TERMINAL

TYPE

DESCRIPTION

NAME

NO.

TYPE

DESCRIPTION

CLK

24

I

Clock input. CLK provides the clock signal to be distributed by the CDC509 clock driver. CLK is used

to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must

have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered

up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the

feedback signal to its reference signal.

FBIN

13

I

Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to

FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is

nominally zero phase error between CLK and FBIN.

1G

11

I

Output bank enable. 1G is the output enable for outputs 1Y(0:4). When 1G is low, outputs 1Y(0:4) are

disabled to a logic-low state. When 1G is high, all outputs 1Y(0:4) are enabled and switch at the same

frequency as CLK.

2G

14

I

Output bank enable. 2G is the output enable for outputs 2Y(0:3). When 2G is low, outputs 2Y(0:3) are

disabled to a logic low state. When 2G is high, all outputs 2Y(0:3) are enabled and switch at the same

frequency as CLK.

FBOUT

12

O

Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as

CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL.

1Y(0:4)

3, 4, 5, 8, 9

O

Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:4) is enabled via

the 1G input. These outputs can be disabled to a logic-low state by deasserting the 1G control input.

2Y(0:3)

16, 17, 20 21

O

Clock outputs. These outputs provide low-skew copies of CLK. Output bank 2Y(0:3) is enabled via

the 2G input. These outputs can be disabled to a logic-low state by deasserting the 2G control input.

AVCC

23

Power

Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC

can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed

and CLK is buffered directly to the device outputs.

AGND

1

Ground

Analog ground. AGND provides the ground reference for the analog circuitry.

VCC

2, 10, 15, 22

Power

Power supply

GND

6, 7, 18, 19

Ground

Ground

−0.5 V to 4.6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

−0.5 V to 6.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

−50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±100 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

0.7 W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

−65

°C to 150°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. This value is limited to 4.6 V maximum.

3. The maximum package power dissipation is calculated using a junction temperature of 150

°C and a board trace length of 750 mils.

For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data

Book, literature number SCBD002.