CDCE913-Q1

CDCEL913-Q1

SCAS918A – JUNE 2013

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

DESCRIPTION

The CDCE913-Q1 and CDCEL913-Q1 are modular PLL-based, low-cost, high-performance, programmable clock

synthesizers, multipliers, and dividers. They generate up to three output clocks from a single input frequency.

Each output can be programmed in-system for any clock frequency up to 230 MHz, using the integrated

configurable PLL.

CDCE913-Q1.

The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load

capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 to 20 pF.

Additionally, a selectable on-chip VCXO allows synchronization of the output frequency to an external control

signal, that is, the PWM signal.

The deep M/N divider ratio allows the generation of zero-ppm audio/video, networking (WLAN, Bluetooth,

Ethernet, GPS) or interface (USB, IEEE1394, memory stick) clocks from, for example, a 27-MHz reference input

frequency.

The PLL supports SSC (spread-spectrum clocking). SSC can be center-spread or down-spread clocking, which

is a common technique to reduce electromagnetic interference (EMI).

Based on the PLL frequency and the divider settings, the internal loop filter components are automatically

adjusted to achieve high stability and optimized jitter transfer characteristics.

The device supports non-volatile EEPROM programming for ease customization of the device to the application.

It is preset to a factory default configuration (see the DEFAULT DEVICE CONFIGURATION section). It can be

re-programmed to a different application configuration before PCB assembly, or re-programmed by in-system

programming. All device settings are programmable through the SDA/SCL bus, a 2-wire serial interface.

Three programmable control inputs, S0, S1, and S2, can be used to select different frequencies, change SSC

setting for lowering EMI, or control other features like outputs disable to low, outputs 3-state, power down, PLL

bypass, etc).

The CDCx913 operates in a 1.8-V environment. It operates in a temperature range of –40° C to 125° C.

Terminal Functions for CDCE913-Q1, CDCEL913-Q1

TERMINAL

I/O

DESCRIPTION

NAME

PIN TSSOP14

GND

5, 10

Ground

Ground

S0

2

I

User-programmable control input S0; LVCMOS inputs; 500-k

Ω internal pullup

SCL: serial clock input LVCMOS (default configuration), internal pullup 500 k

Ω or

SCL/S2

12

I

S2: user-programmable control input; LVCMOS inputs; 500-k

Ω internal pullup

SDA: bidirectional serial data inputoutput (default configuration), LVCMOS internal pullup;

SDA/S1

13

I/O or I

or

S1: user-programmable control input; LVCMOS inputs; 500-k

Ω internal pullup

4

I

VCXO control voltage (leave open or pull up when not used)

3

Power

1.8-V power supply for the device

CDCEL913-Q1: 1.8-V supply for all outputs

6, 7

Power

CDCE913-Q1: 3.3-V or 2.5-V supply for all outputs

XinCLK

1

I

Crystal oscillator input or LVCMOS clock Input (selectable via SDA/SCL bus)

Xout

14

O

Crystal oscillator output (leave open or pull up when not used)

Y1–Y3

11, 9, 8

O

LVCMOS outputs

2

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Product Folder Links: CDCE913-Q1 CDCEL913-Q1