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AD7266ASU Datenblatt(PDF) 11 Page - Analog Devices |
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AD7266ASU Datenblatt(HTML) 11 Page - Analog Devices |
11 / 17 page Preliminary Technical Data AD7266 ANALOG INPUT The channels to be converted on simultaneously are selected via the multiplexer address inputs A0 to A2. The logic states of these pins are also checked upon the falling edge of CS and the channels are chosen for the next conversion. The selected input channels are decoded as shown in Table 6. The analog inputs of the AD7266 may be configured as single ended or true differential via the SGL/DIFF logic pin, as shown in Figure 5. On the falling edge of CS, point A, the logic level of the SGL/DIFF pin is checked to determine the configuration of the analog input channels for the next conversion. If this pin is tied to a logic low, the analog input channels to each on-chip ADC are set up as three true differential pairs. If this pin is at a logic high when CS goes low, the analog input channels to each on-chip ADC are set up as six single-ended analog inputs. In Figure 5 at point A, the SGL/DIFF pin is at a logic high so the analog inputs are configured as single-ended for the next conversion, i.e. sampling point B. At point B, the logic level of the SGL/DIFF pin has changed to low; there fore, the analog inputs are configured as differential for the next conversion after this one, even though this current conversion is on single ended configured inputs. The analog input range of the AD7266 can be selected as 0 V to VREF or 0 V to 2 × VREF via the RANGE pin. This selection is made in a similar fashion to that of the SGL/DIFF pin by checking the logic state of the RANGE pin upon the falling edge of CS. The analog input range is set up for the next conversion. If this pin is tied to a logic low upon the falling edge of CS, the analog input range for the next conversion is 0 V to VREF. If this pin is tied to a logic high upon the falling edge of CS, the analog input range for the next conversion is 0 V to 2 × VREF. OUTPUT CODING The AD7266 output coding is set to either twos complement or straight binary depending on which analog input configuration is selected for a conversion. Table 5 shows which output coding scheme is used for each possible analog input configuration. A CS SCLK SGL/DIFF 114 1 14 B Table 5 AD7266 Output Coding SGL/DIFF Range Output Coding DIFF 0 V to VREF Twos Complement DIFF 0 V to 2 × VREF Twos Complement SGL 0 V to VREF Straight Binary SGL 0 V to 2 × VREF Twos Complement PSUEDO DIFF 0 V to VREF Straight Binary PSUEDO DIFF 0 V to 2 × VREF Twos Complement Figure 5. Selecting Differential or Single Ended Configuration Table 6. Analog Input Type and Channel Selection ADC A ADC B SGL/DIFF A2 A1 A0 VIN+ VIN– VIN+ VIN– Comment 1 0 0 0 VA1 AGND VB1 AGND Single Ended 1 0 0 1 VA2 AGND VB2 AGND Single Ended 1 0 1 0 VA3 AGND VB3 AGND Single Ended 1 0 1 1 VA4 AGND VB4 AGND Single Ended 1 1 0 0 VA5 AGND VB5 AGND Single Ended 1 1 0 1 VA6 AGND VB6 AGND Single Ended 0 0 0 0 VA1 VA2 VB1 VB2 Fully Differential 0 0 0 1 VA1 VA2 VB1 VB2 Pseudodifferential 0 0 1 0 VA3 VA4 VB3 VB4 Fully Differential 0 0 1 1 VA3 VA4 VB3 VB4 Pseudodifferential 0 1 0 0 VA5 VA6 VB5 VB6 Fully Differential 0 1 0 1 VA5 VA6 VB5 VB6 Pseudodifferential Rev. PrG | Page 11 of 17 |
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